Searched refs:regclass_begin (Results 1 – 8 of 8) sorted by relevance
| /external/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 141 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){ in getMinimalPhysRegClass()
171 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), in getAllocatableSet()
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| D | RegisterClassInfo.cpp | 160 RI = TRI->regclass_begin(), RE = TRI->regclass_end(); RI != RE; ++RI) { in computePSetLimit()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 60 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), in ResourcePriorityQueue()
367 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), in regPressureDelta()
374 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), in regPressureDelta()
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| D | ScheduleDAGRRList.cpp | 1674 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), in RegReductionPQBase()
1943 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), in dumpRegPressure()
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| D | TargetLowering.cpp | 2267 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), in getRegForInlineAsmConstraint()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 399 regclass_iterator regclass_begin() const { return Classes; } in regclass_begin() function
403 return (unsigned)(regclass_end()-regclass_begin()); in getNumRegClasses()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 602 regclass_iterator regclass_begin() const { return RegClassBegin; } in regclass_begin() function
606 return (unsigned)(regclass_end()-regclass_begin()); in getNumRegClasses()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 135 for (regclass_iterator I = regclass_begin(), E = regclass_end(); in getRegPressureSetLimit()
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