| /external/llvm/test/CodeGen/MIR/AMDGPU/ |
| D | target-index-operands.mir | 55 …gpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
56 …gpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
57 … %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
58 %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
60 %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
61 %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
62 %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
63 %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
64 %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
65 %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
[all …]
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| D | expected-target-index-name.mir | 47 %sgpr2 = S_ADD_U32 %sgpr2, target-index(0), implicit-def %scc, implicit-def %scc
48 … %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
49 %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
51 %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
52 %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
53 %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
54 %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
55 %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
56 %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
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| D | invalid-target-index-operand.mir | 47 %sgpr2 = S_ADD_U32 %sgpr2, target-index(constdata-start), implicit-def %scc, implicit-def %scc
48 … %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
49 %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
51 %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
52 %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
53 %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
54 %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
55 %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
56 %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
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| /external/openfst/src/include/fst/script/ |
| D | info-impl.h | 135 vector<StateId> scc; variable
138 SccVisitor<Arc> scc_visitor(&scc, &access, &coaccess, &props);
152 for (StateId s = 0; s < scc.size(); ++s) {
159 if (scc[s] >= nscc_)
160 nscc_ = scc[s] + 1;
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| /external/openfst/src/include/fst/ |
| D | rmepsilon.h | 276 vector<StateId> scc; in RmEpsilon() local
277 SccVisitor<Arc> scc_visitor(&scc, 0, 0, &props); in RmEpsilon()
279 vector<StateId> first(scc.size(), kNoStateId); in RmEpsilon()
280 vector<StateId> next(scc.size(), kNoStateId); in RmEpsilon()
281 for (StateId i = 0; i < scc.size(); i++) { in RmEpsilon()
282 if (first[scc[i]] != kNoStateId) in RmEpsilon()
283 next[i] = first[scc[i]]; in RmEpsilon()
284 first[scc[i]] = i; in RmEpsilon()
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| D | queue.h | 447 SccQueue(const vector<StateId> &scc, vector<Queue*> *queue) in SccQueue() argument
448 : QueueBase<S>(SCC_QUEUE), queue_(queue), scc_(scc), front_(0), in SccQueue()
654 const vector<StateId> &scc,
689 const vector<StateId> &scc, in SccQueueType() argument
710 if (scc[state] == scc[arc.nextstate]) { in SccQueueType()
711 QueueType &type = (*queue_type)[scc[state]]; in SccQueueType()
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| D | connect.h | 134 SccVisitor(vector<StateId> *scc, vector<bool> *access, in SccVisitor() argument
136 : scc_(scc), access_(access), coaccess_(coaccess), props_(props) {} in SccVisitor()
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| /external/libxml2/result/schemas/ |
| D | scc-no-xmlns_0_0.err | 1 ./test/schemas/scc-no-xmlns_0.xsd:7: element attribute: Schemas parser error : Element '{http://www…
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| D | scc-no-xsi_0_0.err | 1 ./test/schemas/scc-no-xsi_0.xsd:7: element attribute: Schemas parser error : Element '{http://www.w…
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| /external/llvm/test/Transforms/Inline/ |
| D | gvn-inline-iteration.ll | 1 ; RUN: opt -basicaa -inline -gvn -S -max-cg-scc-iterations=1 < %s | FileCheck %s
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| D | crash2.ll | 1 ; RUN: opt -inline -scalarrepl -max-cg-scc-iterations=1 -disable-output < %s
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIInstructions.td | 614 let DisableEncoding = "$scc" in {
616 0x00000004, (ins brtarget:$target, SCCReg:$scc),
620 0x00000005, (ins brtarget:$target, SCCReg:$scc),
624 } // End DisableEncoding = "$scc"
836 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
837 [(set (i32 SReg_32:$dst), (select SCCReg:$scc, SReg_32:$src0, SReg_32:$src1))]
844 (f32 (select SCCReg:$scc, SReg_32:$src0, SReg_32:$src1)),
845 (S_CSELECT_B32 SReg_32:$src0, SReg_32:$src1, SCCReg:$scc)
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | split-scalar-i64-add.ll | 8 ; scc instead.
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| /external/c-ares/ |
| D | ares_init.c | 103 static char *try_config(char *s, const char *opt, char scc);
1563 static char *try_config(char *s, const char *opt, char scc) in try_config() argument
1578 if(scc) in try_config()
1579 while (*p && (*p != '#') && (*p != scc)) in try_config()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 44 def SCC : SIReg<"scc", 253>;
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| /external/icu/icu4c/source/data/misc/ |
| D | metadata.txt | 984 scc{
|