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Searched refs:setSubReg (Results 1 – 19 of 19) sorted by relevance

/external/llvm/lib/Target/PowerPC/
DPPCVSXFMAMutate.cpp241 MI->getOperand(0).setSubReg(KilledProdSubReg); in processBlock()
242 MI->getOperand(1).setSubReg(KilledProdSubReg); in processBlock()
243 MI->getOperand(3).setSubReg(AddSubReg); in processBlock()
244 MI->getOperand(2).setSubReg(OtherProdSubReg); in processBlock()
DPPCVSXCopy.cpp149 SrcMO.setSubReg(IsVRReg(DstMO.getReg(), MRI) ? PPC::sub_128 : in processBlock()
DPPCInstrInfo.cpp390 MI->getOperand(0).setSubReg(SubReg2); in commuteInstructionImpl()
394 MI->getOperand(2).setSubReg(SubReg1); in commuteInstructionImpl()
395 MI->getOperand(1).setSubReg(SubReg2); in commuteInstructionImpl()
1771 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second); in optimizeCompareInstr()
/external/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp546 Copy->getOperand(0).setSubReg(SubIdx); in INITIALIZE_PASS_DEPENDENCY()
809 MOSrc.setSubReg(NewSubReg); in RewriteCurrentSource()
947 NewCopy->getOperand(0).setSubReg(Def.SubReg); in RewriteSource()
1011 MO.setSubReg(NewSubReg); in RewriteCurrentSource()
1141 MO.setSubReg(NewSubReg); in RewriteCurrentSource()
DTargetInstrInfo.cpp173 MI->getOperand(0).setSubReg(SubReg0); in commuteInstructionImpl()
177 MI->getOperand(Idx2).setSubReg(SubReg1); in commuteInstructionImpl()
178 MI->getOperand(Idx1).setSubReg(SubReg2); in commuteInstructionImpl()
DTwoAddressInstructionPass.cpp1436 SrcMO.setSubReg(0); in collectTiedOperands()
1554 MO.setSubReg(0); in processTiedPairs()
1571 MO.setSubReg(0); in processTiedPairs()
1703 mi->getOperand(0).setSubReg(SubIdx); in runOnMachineFunction()
DVirtRegMap.cpp416 MO.setSubReg(0); in rewrite()
DLiveDebugVariables.cpp806 MO.setSubReg(locations[OldLocNo].getSubReg()); in splitLocation()
928 Loc.setSubReg(0); in rewriteLocations()
DMachineInstr.cpp83 setSubReg(SubIdx); in substVirtReg()
92 setSubReg(0); in substPhysReg()
DRegAllocFast.cpp684 MO.setSubReg(0); in setPhysReg()
DRegisterCoalescer.cpp965 DefMO.setSubReg(0); in reMaterializeTrivialDef()
1001 NewMI->getOperand(0).setSubReg(NewIdx); in reMaterializeTrivialDef()
/external/llvm/include/llvm/CodeGen/
DMachineOperand.h347 void setSubReg(unsigned subReg) { in setSubReg() function
619 Op.setSubReg(SubReg);
/external/llvm/lib/Target/Hexagon/
DHexagonExpandCondsets.cpp474 ImpUse.setSubReg(Defs[i].Sub); in addInstrToLiveness()
957 Op.setSubReg(RN.Sub); in renameInRange()
DHexagonBitSimplify.cpp350 I->setSubReg(NewSR); in replaceRegWithSub()
368 I->setSubReg(NewSR); in replaceSubWithSub()
1838 ValOp.setSubReg(H.Sub); in genStoreUpperHalf()
DHexagonSplitDouble.cpp1069 Op.setSubReg(0); in replaceSubregUses()
DHexagonHardwareLoops.cpp1882 MO.setSubReg(PredRSub); in createPreheaderForLoop()
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp960 Src1.setSubReg(SubReg); in commuteInstructionImpl()
1102 Src0->setSubReg(Src1SubReg); in FoldImmediate()
1106 Src1->setSubReg(Src2SubReg); in FoldImmediate()
1912 Src0.setSubReg(Src1.getSubReg()); in legalizeOperandsVOP2()
1917 Src1.setSubReg(Src0SubReg); in legalizeOperandsVOP2()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp927 MIB->getOperand(0).setSubReg(Mips::sub_32); in insertDivByZeroTrap()
/external/llvm/lib/Target/X86/
DX86InstrInfo.cpp5644 NewMI->getOperand(0).setSubReg(X86::sub_32bit); in foldMemoryOperandImpl()