| /external/boringssl/src/crypto/curve25519/asm/ |
| D | x25519-asm-x86_64.S | 265 shld $13,%r8,%r9 label
267 shld $13,%r10,%r11 label
270 shld $13,%r12,%r13 label
273 shld $13,%r14,%r15 label
276 shld $13,%rbx,%rbp label
407 shld $13,%rcx,%r8 label
409 shld $13,%r9,%r10 label
412 shld $13,%r11,%r12 label
415 shld $13,%r13,%r14 label
418 shld $13,%r15,%rbx label
[all …]
|
| /external/boringssl/win-x86_64/crypto/sha/ |
| D | sha1-x86_64.asm | 2528 shld eax,eax,5
2542 shld ebp,ebp,5
2556 shld edx,edx,5
2571 shld ecx,ecx,5
2583 shld ebx,ebx,5
2597 shld eax,eax,5
2611 shld ebp,ebp,5
2626 shld edx,edx,5
2639 shld ecx,ecx,5
2653 shld ebx,ebx,5
[all …]
|
| /external/boringssl/win-x86/crypto/sha/ |
| D | sha1-586.asm | 2697 shld eax,eax,5
2712 shld edi,edi,5
2725 shld edx,edx,5
2739 shld ecx,ecx,5
2754 shld ebx,ebx,5
2769 shld eax,eax,5
2782 shld edi,edi,5
2796 shld edx,edx,5
2811 shld ecx,ecx,5
2826 shld ebx,ebx,5
[all …]
|
| /external/llvm/test/CodeGen/X86/ |
| D | 2006-01-19-ISelFoldingBug.ll | 2 ; RUN: grep shld | count 1
4 ; Check that the isel does not fold the shld, which already folds a load
|
| D | x86-64-double-shifts-Oz-Os-O2.ll | 4 ; Verify that we generate shld insruction when we are optimizing for size,
26 ; Verify that we generate shld insruction when we are optimizing for size,
47 ; Verify that we do not generate shld insruction when we are not optimizing
|
| D | x86-64-double-shifts-var.ll | 20 ; double precision shift instructions we do not generate 'shld' or 'shrd'
30 ; CHECK-NOT: shld
|
| D | shift-coalesce.ll | 2 ; RUN: grep "shld.*cl"
|
| D | x86-64-double-precision-shift-left.ll | 4 ; of instructions with lower latencies instead of shld instruction.
|
| D | rot64.ll | 4 ; RUN: grep shld %t | count 2
|
| /external/llvm/test/MC/X86/ |
| D | intel-syntax.s | 377 shld DX, BX define
378 shld DX, BX, CL define
379 shld DX, BX, 1 define
380 shld [RAX], BX label
381 shld [RAX], BX, CL label
|
| D | x86-64.s | 357 shld %bx, %dx label
358 shld %cl, %bx, %dx label
359 shld $1, %bx, %dx label
360 shld %bx, (%rax) label
361 shld %cl, %bx, (%rax) label
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrShiftRotate.td | 693 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
705 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
715 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
731 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
745 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
759 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
776 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
785 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
794 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
805 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
|
| D | X86InstrInfo.td | 2960 // shld/shrd op,op -> shld op, op, CL
2961 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2962 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2963 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2968 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2969 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2970 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
|
| D | X86.td | 97 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
|
| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 648 #define SHLD_L(a,b,c) CHOICE(shldl ARG3(a,b,c), shldl ARG3(a,b,c), _LTOG shld ARG3(c,b,a))
649 #define SHLD2_L(a,b) CHOICE(shldl ARG2(a,b), shldl ARG3(CL,a,b), _LTOG shld ARG3(b,a,CL))
650 #define SHLD_W(a,b,c) CHOICE(shldw ARG3(a,b,c), shldw ARG3(a,b,c), _WTOG shld ARG3(c,b,a))
651 #define SHLD2_W(a,b) CHOICE(shldw ARG2(a,b), shldw ARG3(CL,a,b), _WTOG shld ARG3(b,a,CL))
1369 #define SHLD_L(a,b,c) shld
1370 #define SHLD2_L(a,b) shld L_(b), L_(a)
1371 #define SHLD_W(a,b,c) shld
1372 #define SHLD2_W(a,b) shld W_(b), W_(a)
|
| /external/valgrind/docs/internals/ |
| D | 3_1_BUGSTATUS.txt | 68 vx1615 fixed 126583 amd64->IR: 0x48 0xF 0xA4 0xC2 (shld $1,%rax,%rdx)
|
| /external/libvpx/libvpx/third_party/libyuv/source/ |
| D | scale_win.cc | 1326 shld edx, eax, 16 // 32.16 in FixedDiv_X86()
1340 shld edx, eax, 16 // 32.16 in FixedDiv1_X86()
|
| /external/v8/test/cctest/ |
| D | test-disasm-x87.cc | 123 __ shld(edx, ecx, 10); in TEST() local
|
| D | test-disasm-x64.cc | 120 __ shld(rdx, rcx); in TEST() local
222 __ shld(rdx, rbx); in TEST() local
|
| D | test-disasm-ia32.cc | 123 __ shld(edx, ecx, 10); in TEST() local
|
| /external/libyuv/files/source/ |
| D | scale_win.cc | 1346 shld edx, eax, 16 // 32.16 in FixedDiv_X86()
1360 shld edx, eax, 16 // 32.16 in FixedDiv1_X86()
|
| /external/v8/src/x87/ |
| D | assembler-x87.h | 760 void shld(Register dst, Register src, uint8_t shift);
|
| /external/valgrind/VEX/test/ |
| D | test-amd64.c | 142 #define OP shld
|
| D | test-i386.c | 131 #define OP shld
|
| /external/elfutils/libcpu/defs/ |
| D | i386 | 518 00001111,10100100,{mod}{reg}{r_m},{imm8}:shld {imm8},{reg},{mod}{r_m}
519 00001111,10100101,{mod}{reg}{r_m}:shld %cl,{reg},{mod}{r_m}
|