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Searched refs:simm13 (Results 1 – 9 of 9) sorted by relevance

/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td344 // inc simm13, rd -> add rd, simm13, rd
345 def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
350 // inccc simm13, rd -> addcc rd, simm13, rd
351 def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
356 // dec simm13, rd -> sub rd, simm13, rd
357 def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
362 // deccc simm13, rd -> subcc rd, simm13, rd
363 def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
367 def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, i32imm:$simm13), 0>;
371 def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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DSparcInstr64Bit.td64 // The ALU instructions want their simm13 operands as i32 immediates.
68 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
99 // (sllx simm13, n)
103 // (xor (sllx sethi), simm13)
104 // (sllx (xor sethi, simm13))
113 // (or (sllx sethi), (or sethi, simm13))
114 // (xnor (sllx sethi), (or sethi, simm13))
120 // (or (sllx (or sethi, simmm13)), (or sethi, simm13))
180 def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
197 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
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DSparcInstrInfo.td64 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
257 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
258 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
259 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
269 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
270 !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
369 let rd = 0, rs1 = 1, simm13 = 3 in
542 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
543 "andn $rs1, $simm13, $rd", []>;
552 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
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DSparcInstrFormats.td137 bits<13> simm13;
143 let Inst{12-0} = simm13;
/external/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp325 unsigned simm13 = 0; in DecodeMem() local
327 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeMem()
345 MI.addOperand(MCOperand::createImm(simm13)); in DecodeMem()
456 unsigned simm13 = 0; in DecodeJMPL() local
458 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeJMPL()
474 MI.addOperand(MCOperand::createImm(simm13)); in DecodeJMPL()
489 unsigned simm13 = 0; in DecodeReturn() local
491 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeReturn()
502 MI.addOperand(MCOperand::createImm(simm13)); in DecodeReturn()
520 unsigned simm13 = 0; in DecodeSWAP() local
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/external/valgrind/VEX/priv/
Dhost_arm_defs.h140 Int simm13; /* -4095 .. +4095 */ member
151 extern ARMAMode1* ARMAMode1_RI ( HReg reg, Int simm13 );
Dhost_arm_defs.c205 ARMAMode1* ARMAMode1_RI ( HReg reg, Int simm13 ) { in ARMAMode1_RI() argument
209 am->ARMam1.RI.simm13 = simm13; in ARMAMode1_RI()
210 vassert(-4095 <= simm13 && simm13 <= 4095); in ARMAMode1_RI()
226 vex_printf("%d(", am->ARMam1.RI.simm13); in ppARMAMode1()
2933 if (am->ARMam1.RI.simm13 < 0) { in do_load_or_store32()
2935 simm12 = -am->ARMam1.RI.simm13; in do_load_or_store32()
2938 simm12 = am->ARMam1.RI.simm13; in do_load_or_store32()
3090 if (am->ARMam1.RI.simm13 < 0) { in emit_ARMInstr()
3092 simm12 = -am->ARMam1.RI.simm13; in emit_ARMInstr()
3095 simm12 = am->ARMam1.RI.simm13; in emit_ARMInstr()
Dhost_arm_isel.c743 && am->ARMam1.RI.simm13 >= -4095 in sane_AMode1()
744 && am->ARMam1.RI.simm13 <= 4095 ); in sane_AMode1()
/external/llvm/docs/
DWritingAnLLVMBackend.rst816 [(set i32:$dst, (OpNode i32:$b, simm13:$c))]>;