| /external/llvm/test/CodeGen/ARM/ |
| D | 2011-08-29-SchedCycle.ll | 3 ; When a i64 sub is expanded to subc + sube.
10 ; sube
22 ; sube
24 ; However since subc and sube are "glued" together, this ends up being a
25 ; cycle when the scheduler combine subc and sube as a single scheduling
30 ; fix subc / sube (and addc / adde) to use physical register dependency instead.
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| /external/libpng/scripts/ |
| D | options.awk | 52 sube=" \"@" # Substitute end
843 deflt = " " subs substr(deflt, 3) sube
864 print def i, subs "PNG_" i sube end >out
868 print def i, subs "PNG_set_" i sube end >out
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.td | 870 [(set GR8:$dst, (sube GR8:$src, GR8:$src2)),
875 [(set GR16:$dst, (sube GR16:$src, GR16:$src2)),
881 [(set GR8:$dst, (sube GR8:$src, imm:$src2)),
886 [(set GR16:$dst, (sube GR16:$src, imm:$src2)),
892 [(set GR8:$dst, (sube GR8:$src, (load addr:$src2))),
897 [(set GR16:$dst, (sube GR16:$src, (load addr:$src2))),
904 [(store (sube (load addr:$dst), GR8:$src), addr:$dst),
909 [(store (sube (load addr:$dst), GR16:$src), addr:$dst),
915 [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
920 [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
[all …]
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| /external/apache-xml/src/main/java/org/apache/xml/serializer/ |
| D | HTMLEntities.properties | 250 sube=8838 key
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.td | 814 def SLBR : BinaryRRE<"slb", 0xB999, sube, GR32, GR32>;
815 def SLGBR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;
818 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>;
819 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 516 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
519 [(set i64:$rT, (sube -1, i64:$rA))]>;
522 [(set i64:$rT, (sube 0, i64:$rA))]>;
|
| D | PPCInstrInfo.td | 2426 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2429 [(set i32:$rT, (sube -1, i32:$rA))]>;
2432 [(set i32:$rT, (sube 0, i32:$rA))]>;
|
| /external/llvm/include/llvm/Target/ |
| D | Target.td | 262 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
266 // let SubRegIndices = [sube, subo] in {
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| D | TargetSelectionDAG.td | 392 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 330 def SubCCCV4I32 : VecBinaryOp<V4AsmStr<"subc.cc.s32">, sube, V4I32Regs,
332 def SubCCCV2I32 : VecBinaryOp<V2AsmStr<"subc.cc.s32">, sube, V2I32Regs,
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| D | NVPTXInstrInfo.td | 403 defm SUBCCC : ADD_SUB_INT_32<"subc.cc", sube>;
|
| /external/v8/src/ppc/ |
| D | assembler-ppc.h | 815 void sube(Register dst, Register src1, Register src2, OEBit s = LeaveOE,
|
| D | assembler-ppc.cc | 894 void Assembler::sube(Register dst, Register src1, Register src2, OEBit o, in sube() function in v8::internal::Assembler
|
| /external/v8/src/compiler/ppc/ |
| D | code-generator-ppc.cc | 1062 __ sube(i.OutputRegister(1), i.InputRegister(1), i.InputRegister(3)); in AssembleArchInstruction() local
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 1162 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>,
|
| D | ARMInstrInfo.td | 1562 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 600 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 229 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
|
| /external/chromium-trace/catapult/third_party/vinn/third_party/parse5/test/data/tokenization/ |
| D | namedEntities.test | 38783 "input": "&sube",
38784 "description": "Bad named entity: sube without a semi-colon",
38789 "&sube"
38794 "input": "⊆",
38795 "description": "Named entity: sube; with a semi-colon",
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| /external/icu/icu4j/main/shared/data/ |
| D | Transliterator_Han_Latin_EDICT.txt | 43491 術 < sube\ ;
104363 術 > sube\ ;
|