| /external/llvm/test/CodeGen/Mips/ |
| D | divrem.ll | 35 ; ACC32-TRAP: teq $5, $zero, 7
38 ; ACC64-TRAP: teq $5, $zero, 7
41 ; GPR32-TRAP: teq $5, $zero, 7
44 ; GPR64-TRAP: teq $5, $zero, 7
46 ; NOCHECK-NOT: teq
62 ; ACC32-TRAP: teq $5, $zero, 7
65 ; ACC64-TRAP: teq $5, $zero, 7
68 ; GPR32-TRAP: teq $5, $zero, 7
71 ; GPR64-TRAP: teq $5, $zero, 7
73 ; NOCHECK-NOT: teq
[all …]
|
| D | mips64instrs.ll | 120 ; ACCMULDIV: teq $[[T1]], $zero, 7
124 ; GPRMULDIV: teq $[[T1]], $zero, 7
141 ; ACCMULDIV: teq $[[T1]], $zero, 7
145 ; GPRMULDIV: teq $[[T1]], $zero, 7
158 ; ACCMULDIV: teq $5, $zero, 7
162 ; GPRMULDIV: teq $5, $zero, 7
173 ; ACCMULDIV: teq $5, $zero, 7
177 ; GPRMULDIV: teq $5, $zero, 7
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | udiv.ll | 33 ; NOT-R6: teq $5, $zero, 7
37 ; R6: teq $5, $zero, 7
48 ; NOT-R6: teq $5, $zero, 7
52 ; R6: teq $5, $zero, 7
63 ; NOT-R6: teq $5, $zero, 7
67 ; R6: teq $5, $zero, 7
78 ; NOT-R6: teq $5, $zero, 7
82 ; R6: teq $5, $zero, 7
95 ; GP64-NOT-R6: teq $5, $zero, 7
99 ; 64R6: teq $5, $zero, 7
|
| D | srem.ll | 36 ; NOT-R6: teq $5, $zero, 7
42 ; R6: teq $5, $zero, 7
55 ; NOT-R2-R6: teq $5, $zero, 7
61 ; R2-R5: teq $5, $zero, 7
66 ; R6: teq $5, $zero, 7
78 ; NOT-R2-R6: teq $5, $zero, 7
84 ; R2-R5: teq $5, $zero, 7
89 ; R6: teq $5, $zero, 7
101 ; NOT-R6: teq $5, $zero, 7
105 ; R6: teq $5, $zero, 7
[all …]
|
| D | sdiv.ll | 33 ; NOT-R6: teq $5, $zero, 7
40 ; R6: teq $5, $zero, 7
54 ; NOT-R2-R6: teq $5, $zero, 7
61 ; R2-R5: teq $5, $zero, 7
67 ; R6: teq $5, $zero, 7
80 ; NOT-R2-R6: teq $5, $zero, 7
87 ; R2-R5: teq $5, $zero, 7
93 ; R6: teq $5, $zero, 7
106 ; NOT-R6: teq $5, $zero, 7
110 ; R6: teq $5, $zero, 7
[all …]
|
| D | urem.ll | 38 ; NOT-R6: teq $[[T0]], $zero, 7
46 ; R6: teq $[[T0]], $zero, 7
61 ; NOT-R2-R6: teq $[[T0]], $zero, 7
69 ; R2-R5: teq $[[T0]], $zero, 7
76 ; R6: teq $[[T0]], $zero, 7
90 ; NOT-R2-R6: teq $[[T0]], $zero, 7
98 ; R2-R5: teq $[[T0]], $zero, 7
105 ; R6: teq $[[T0]], $zero, 7
117 ; NOT-R6: teq $5, $zero, 7
121 ; R6: teq $5, $zero, 7
[all …]
|
| /external/llvm/test/MC/Mips/ |
| D | macro-ddiv.s | 52 # CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
58 # CHECK-TRAP: teq $25, $1, 6 # encoding: [0x03,0x21,0x01,0xb4]
62 # CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4]
68 # CHECK-TRAP: teq $24, $1, 6 # encoding: [0x03,0x01,0x01,0xb4]
72 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
75 # CHECK-TRAP: teq $9, $zero, 7 # encoding: [0x01,0x20,0x01,0xf4]
81 # CHECK-TRAP: teq $zero, $1, 6 # encoding: [0x00,0x01,0x01,0xb4]
85 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
| D | mips-control-instructions.s | 20 # CHECK32: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
21 # CHECK32: teq $zero, $3, 1 # encoding: [0x00,0x03,0x00,0x74]
53 # CHECK64: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
54 # CHECK64: teq $zero, $3, 1 # encoding: [0x00,0x03,0x00,0x74]
89 teq $0,$3
90 teq $0,$3,1
|
| D | macro-div.s | 40 # CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
45 # CHECK-TRAP: teq $25, $1, 6 # encoding: [0x03,0x21,0x01,0xb4]
49 # CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4]
54 # CHECK-TRAP: teq $24, $1, 6 # encoding: [0x03,0x01,0x01,0xb4]
58 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
| D | macro-ddivu.s | 37 # CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
42 # CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4]
47 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
52 # CHECK-TRAP: teq $9, $zero, 7 # encoding: [0x01,0x20,0x01,0xf4]
57 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
| D | micromips-trap-instructions.s | 12 # CHECK-EL: teq $8, $9 # encoding: [0x28,0x01,0x3c,0x00]
27 # CHECK-EB: teq $8, $9 # encoding: [0x01,0x28,0x00,0x3c]
39 teq $8, $9, 0
|
| D | macro-divu.s | 31 # CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
36 # CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4]
41 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | thumb2-teq2.ll | 8 ; CHECK: teq.w {{.*}}, r1
16 ; CHECK: teq.w {{.*}}, r1
24 ; CHECK: teq.w {{.*}}, r1, lsl #5
33 ; CHECK: teq.w {{.*}}, r1, lsr #6
42 ; CHECK: teq.w {{.*}}, r1, asr #7
51 ; CHECK: teq.w {{.*}}, {{.*}}, ror #8
|
| D | thumb2-teq.ll | 13 ; CHECK: teq.w {{.*}}, #187
22 ; CHECK: teq.w {{.*}}, #11141290
31 ; CHECK: teq.w {{.*}}, #-872363008
40 ; CHECK: teq.w {{.*}}, #-572662307
56 ; CHECK: teq.w {{.*}}, #1114112
|
| /external/selinux/policycoreutils/sepolicy/ |
| D | search.c | 223 apol_terule_query_t *teq = NULL; in perform_te_query() local
241 teq = apol_terule_query_create(); in perform_te_query()
242 if (!teq) { in perform_te_query()
248 apol_terule_query_set_rules(policy, teq, rules); in perform_te_query()
249 apol_terule_query_set_regex(policy, teq, opt->useregex); in perform_te_query()
252 apol_terule_query_set_source(policy, teq, opt->src_name, opt->indirect); in perform_te_query()
254 apol_terule_query_set_target(policy, teq, opt->tgt_name, opt->indirect); in perform_te_query()
256 apol_terule_query_set_bool(policy, teq, opt->bool_name); in perform_te_query()
259 if (apol_terule_query_append_class(policy, teq, opt->class_name)) { in perform_te_query()
269 if (apol_terule_query_append_class(policy, teq, class_name)) { in perform_te_query()
[all …]
|
| /external/llvm/test/MC/Mips/mips2/ |
| D | valid.s | 148 … teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
149 … teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | rem1.ll | 25 ; CHECK_DAG: teq $[[K]], $zero, 7
48 ; CHECK_DAG: teq $[[K]], $zero, 7
|
| D | div1.ll | 25 ; CHECK_DAG: teq $[[K]], $zero, 7
47 ; CHECK_DAG: teq $[[K]], $zero, 7
|
| /external/llvm/test/MC/Mips/mips32/ |
| D | valid.s | 178 … teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
179 … teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| D | invalid.s | 55 teq $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
56 teq $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
57 …teq $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of ran…
73 teq $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/CodeGen/ARM/ |
| D | tst_teq.ll | 20 ; CHECK: teq
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| D | valid.s | 215 … teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
216 … teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| D | valid.s | 216 … teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
217 … teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
|
| /external/llvm/test/MC/Mips/mips3/ |
| D | valid.s | 212 … teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
213 … teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| D | valid.s | 215 … teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
216 … teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
|