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Searched refs:tiling (Results 1 – 25 of 107) sorted by relevance

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/external/mesa3d/src/mesa/drivers/dri/intel/
Dintel_regions.c136 if (region->tiling != I915_TILING_NONE) in intel_region_map()
156 if (region->tiling != I915_TILING_NONE) in intel_region_unmap()
171 uint32_t tiling, drm_intel_bo *buffer) in intel_region_alloc_internal() argument
185 region->tiling = tiling; in intel_region_alloc_internal()
194 uint32_t tiling, in intel_region_alloc() argument
208 &tiling, &aligned_pitch, flags); in intel_region_alloc()
213 aligned_pitch / cpp, tiling, buffer); in intel_region_alloc()
247 uint32_t bit_6_swizzle, tiling; in intel_region_alloc_for_handle() local
266 ret = drm_intel_bo_get_tiling(buffer, &tiling, &bit_6_swizzle); in intel_region_alloc_for_handle()
275 width, height, pitch, tiling, buffer); in intel_region_alloc_for_handle()
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Dintel_tex_copy.c108 if (intelImage->mt->region->tiling == I915_TILING_Y) { in intel_copy_texsubimage()
127 region->tiling, in intel_copy_texsubimage()
131 intelImage->mt->region->tiling, in intel_copy_texsubimage()
Dintel_screen.c386 uint32_t tiling; in intel_create_image() local
389 tiling = I915_TILING_X; in intel_create_image()
393 tiling = I915_TILING_NONE; in intel_create_image()
399 intel_region_alloc(intelScreen, tiling, cpp, width, height, true); in intel_create_image()
564 image->region->tiling = parent->region->tiling; in intel_from_planar()
893 uint32_t tiling = I915_TILING_X; in intel_detect_swizzling() local
898 &tiling, &aligned_pitch, flags); in intel_detect_swizzling()
902 drm_intel_bo_get_tiling(buffer, &tiling, &swizzle_mode); in intel_detect_swizzling()
Dintel_regions.h70 uint32_t tiling; /**< Which tiling mode the region is in */ member
81 uint32_t tiling,
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_regions.c136 if (region->tiling != I915_TILING_NONE) in intel_region_map()
156 if (region->tiling != I915_TILING_NONE) in intel_region_unmap()
171 uint32_t tiling, drm_intel_bo *buffer) in intel_region_alloc_internal() argument
185 region->tiling = tiling; in intel_region_alloc_internal()
194 uint32_t tiling, in intel_region_alloc() argument
208 &tiling, &aligned_pitch, flags); in intel_region_alloc()
213 aligned_pitch / cpp, tiling, buffer); in intel_region_alloc()
247 uint32_t bit_6_swizzle, tiling; in intel_region_alloc_for_handle() local
266 ret = drm_intel_bo_get_tiling(buffer, &tiling, &bit_6_swizzle); in intel_region_alloc_for_handle()
275 width, height, pitch, tiling, buffer); in intel_region_alloc_for_handle()
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Dintel_tex_copy.c108 if (intelImage->mt->region->tiling == I915_TILING_Y) { in intel_copy_texsubimage()
127 region->tiling, in intel_copy_texsubimage()
131 intelImage->mt->region->tiling, in intel_copy_texsubimage()
Dintel_screen.c386 uint32_t tiling; in intel_create_image() local
389 tiling = I915_TILING_X; in intel_create_image()
393 tiling = I915_TILING_NONE; in intel_create_image()
399 intel_region_alloc(intelScreen, tiling, cpp, width, height, true); in intel_create_image()
564 image->region->tiling = parent->region->tiling; in intel_from_planar()
893 uint32_t tiling = I915_TILING_X; in intel_detect_swizzling() local
898 &tiling, &aligned_pitch, flags); in intel_detect_swizzling()
902 drm_intel_bo_get_tiling(buffer, &tiling, &swizzle_mode); in intel_detect_swizzling()
Dintel_clear.c135 if (stencilRegion->tiling == I915_TILING_Y || in intelClear()
155 if (irb->tiling == I915_TILING_Y || tri_mask & BUFFER_BIT_STENCIL) in intelClear()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dintel_regions.c136 if (region->tiling != I915_TILING_NONE) in intel_region_map()
156 if (region->tiling != I915_TILING_NONE) in intel_region_unmap()
171 uint32_t tiling, drm_intel_bo *buffer) in intel_region_alloc_internal() argument
185 region->tiling = tiling; in intel_region_alloc_internal()
194 uint32_t tiling, in intel_region_alloc() argument
208 &tiling, &aligned_pitch, flags); in intel_region_alloc()
213 aligned_pitch / cpp, tiling, buffer); in intel_region_alloc()
247 uint32_t bit_6_swizzle, tiling; in intel_region_alloc_for_handle() local
266 ret = drm_intel_bo_get_tiling(buffer, &tiling, &bit_6_swizzle); in intel_region_alloc_for_handle()
275 width, height, pitch, tiling, buffer); in intel_region_alloc_for_handle()
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Dintel_tex_copy.c108 if (intelImage->mt->region->tiling == I915_TILING_Y) { in intel_copy_texsubimage()
127 region->tiling, in intel_copy_texsubimage()
131 intelImage->mt->region->tiling, in intel_copy_texsubimage()
Dintel_screen.c386 uint32_t tiling; in intel_create_image() local
389 tiling = I915_TILING_X; in intel_create_image()
393 tiling = I915_TILING_NONE; in intel_create_image()
399 intel_region_alloc(intelScreen, tiling, cpp, width, height, true); in intel_create_image()
564 image->region->tiling = parent->region->tiling; in intel_from_planar()
893 uint32_t tiling = I915_TILING_X; in intel_detect_swizzling() local
898 &tiling, &aligned_pitch, flags); in intel_detect_swizzling()
902 drm_intel_bo_get_tiling(buffer, &tiling, &swizzle_mode); in intel_detect_swizzling()
Dgen7_wm_surface_state.c65 gen7_set_surface_tiling(struct gen7_surface_state *surf, uint32_t tiling) in gen7_set_surface_tiling() argument
67 switch (tiling) { in gen7_set_surface_tiling()
113 assert(mcs_mt->region->tiling == I915_TILING_Y); in gen7_set_surface_mcs_info()
342 gen7_set_surface_tiling(surf, intelObj->mt->region->tiling); in gen7_update_texture_surface()
566 gen7_set_surface_tiling(surf, region->tiling); in gen7_update_renderbuffer_surface()
/external/drm_gralloc/
Dgralloc_drm_radeon.c81 static int radeon_get_pitch_align(struct radeon_info *info, int bpe, uint32_t tiling) in radeon_get_pitch_align() argument
86 if (tiling & RADEON_TILING_MACRO) { in radeon_get_pitch_align()
92 } else if (tiling & RADEON_TILING_MICRO) { in radeon_get_pitch_align()
112 if (tiling) in radeon_get_pitch_align()
122 static int radeon_get_height_align(struct radeon_info *info, uint32_t tiling) in radeon_get_height_align() argument
127 if (tiling & RADEON_TILING_MACRO) in radeon_get_height_align()
129 else if (tiling & RADEON_TILING_MICRO) in radeon_get_height_align()
135 if (tiling) in radeon_get_height_align()
146 int bpe, uint32_t tiling) in radeon_get_base_align() argument
148 int pixel_align = radeon_get_pitch_align(info, bpe, tiling); in radeon_get_base_align()
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Dgralloc_drm_intel.c71 uint32_t tiling; member
243 uint32_t *tiling, unsigned long *stride) in alloc_ibo() argument
275 *tiling = I915_TILING_X; in alloc_ibo()
278 *tiling = I915_TILING_NONE; in alloc_ibo()
287 bpp, tiling, stride, flags); in alloc_ibo()
294 if (*tiling != I915_TILING_NONE) { in alloc_ibo()
296 *tiling = I915_TILING_NONE; in alloc_ibo()
309 *tiling = I915_TILING_NONE; in alloc_ibo()
313 *tiling = I915_TILING_X; in alloc_ibo()
315 *tiling = I915_TILING_NONE; in alloc_ibo()
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/external/libdrm/tegra/
Dtegra.c341 struct drm_tegra_bo_tiling *tiling) in drm_tegra_bo_get_tiling() argument
358 if (tiling) { in drm_tegra_bo_get_tiling()
359 tiling->mode = args.mode; in drm_tegra_bo_get_tiling()
360 tiling->value = args.value; in drm_tegra_bo_get_tiling()
367 const struct drm_tegra_bo_tiling *tiling) in drm_tegra_bo_set_tiling() argument
378 args.mode = tiling->mode; in drm_tegra_bo_set_tiling()
379 args.value = tiling->value; in drm_tegra_bo_set_tiling()
Dtegra.h61 struct drm_tegra_bo_tiling *tiling);
63 const struct drm_tegra_bo_tiling *tiling);
/external/mesa3d/src/gallium/winsys/i915/drm/
Di915_drm_buffer.c58 enum i915_winsys_buffer_tile *tiling, in i915_drm_buffer_create_tiled() argument
64 uint32_t tiling_mode = *tiling; in i915_drm_buffer_create_tiled()
82 *tiling = tiling_mode; in i915_drm_buffer_create_tiled()
94 enum i915_winsys_buffer_tile *tiling, in i915_drm_buffer_from_handle() argument
115 *tiling = tile; in i915_drm_buffer_from_handle()
/external/mesa3d/src/gallium/drivers/i915/
Di915_state_static.c79 buf_3d_tiling_bits(enum i915_winsys_buffer_tile tiling) in buf_3d_tiling_bits() argument
83 switch (tiling) { in buf_3d_tiling_bits()
110 buf_3d_tiling_bits(tex->tiling); in update_framebuffer()
135 buf_3d_tiling_bits(tex->tiling); in update_framebuffer()
219 if (is->is_i945 && tex->tiling != I915_TILE_NONE in update_dst_buf_vars()
Di915_resource_texture.c178 if (!is->debug.tiling) in i915_texture_tiling()
216 tex->tiling = I915_TILE_X; in i9x5_scanout_layout()
254 tex->tiling = I915_TILE_X; in i9x5_display_target_layout()
959 tex->tiling = I915_TILE_NONE; in i915_texture_create()
961 tex->tiling = i915_texture_tiling(is, tex); in i915_texture_create()
982 &tex->tiling, buf_usage); in i915_texture_create()
989 tex->total_nblocksy, get_tiling_string(tex->tiling)); in i915_texture_create()
1008 enum i915_winsys_buffer_tile tiling; in i915_texture_from_handle() local
1012 buffer = iws->buffer_from_handle(iws, whandle, &tiling, &stride); in i915_texture_from_handle()
1032 tex->tiling = tiling; in i915_texture_from_handle()
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Di915_winsys.h160 enum i915_winsys_buffer_tile *tiling,
172 enum i915_winsys_buffer_tile *tiling,
Di915_state_sampler.c278 ms3_tiling_bits(enum i915_winsys_buffer_tile tiling) in ms3_tiling_bits() argument
282 switch (tiling) { in ms3_tiling_bits()
325 | ms3_tiling_bits(tex->tiling)); in update_map()
/external/mesa3d/src/gallium/winsys/i915/sw/
Di915_sw_buffer.c33 enum i915_winsys_buffer_tile *tiling, in i915_sw_buffer_create_tiled() argument
44 buf->tiling = *tiling; in i915_sw_buffer_create_tiled()
/external/deqp/external/vulkancts/framework/vulkan/
DvkQueryUtil.cpp110 …lDevice physicalDevice, VkFormat format, VkImageType type, VkImageTiling tiling, VkImageUsageFlags… in getPhysicalDeviceImageFormatProperties() argument
116 …VK_CHECK(vk.getPhysicalDeviceImageFormatProperties(physicalDevice, format, type, tiling, usage, fl… in getPhysicalDeviceImageFormatProperties()
120 …at, VkImageType type, VkSampleCountFlagBits samples, VkImageUsageFlags usage, VkImageTiling tiling) in getPhysicalDeviceSparseImageFormatProperties() argument
125 …parseImageFormatProperties(physicalDevice, format, type, samples, usage, tiling, &numProp, DE_NULL… in getPhysicalDeviceSparseImageFormatProperties()
130 …parseImageFormatProperties(physicalDevice, format, type, samples, usage, tiling, &numProp, &proper… in getPhysicalDeviceSparseImageFormatProperties()
/external/mesa3d/src/mesa/drivers/dri/r200/
Dradeon_mipmap_tree.h94 …stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, unsigned target);
101 unsigned tiling);
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_mipmap_tree.h94 …stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, unsigned target);
101 unsigned tiling);

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