| /external/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-vmx.txt | 40 0x10 0x43 0x23 0x0e
43 0x10 0x43 0x21 0x8e
46 0x10 0x43 0x21 0x0e
49 0x10 0x43 0x21 0xce
52 0x10 0x43 0x21 0x4e
55 0x10 0x43 0x20 0x0e
58 0x10 0x43 0x20 0x8e
61 0x10 0x43 0x20 0x4e
64 0x10 0x43 0x20 0xce
67 0x10 0x40 0x1b 0x4e
[all …]
|
| D | qpx.txt | 4 0x10 0x60 0x2a 0x10
7 0x10 0x64 0x28 0x2a
13 0x10 0x64 0x2a 0x08
16 0x10 0x64 0x28 0x88
19 0x10 0x60 0x2e 0x9c
25 0x10 0x60 0x2f 0x9c
31 0x10 0x63 0x18 0x08
34 0x10 0x64 0x28 0x10
37 0x10 0x64 0x22 0x88
40 0x10 0x60 0x2e 0x5c
[all …]
|
| D | ppc64-encoding-p8vector.txt | 4 0x10 0x43 0x25 0xce
7 0x10 0x43 0x25 0x4e
10 0x10 0x43 0x24 0xce
13 0x10 0x43 0x24 0x4e
16 0x10 0x40 0x1e 0x4e
19 0x10 0x40 0x1e 0xce
|
| /external/bouncycastle/bcprov/src/main/java/org/bouncycastle/crypto/engines/ |
| D | RC2Engine.java | 210 int x76, x54, x32, x10; in encryptBlock() local
215 x10 = ((in[inOff + 1] & 0xff) << 8) + (in[inOff + 0] & 0xff); in encryptBlock()
219 x10 = rotateWordLeft(x10 + (x32 & ~x76) + (x54 & x76) + workingKey[i ], 1); in encryptBlock()
220 x32 = rotateWordLeft(x32 + (x54 & ~x10) + (x76 & x10) + workingKey[i+1], 2); in encryptBlock()
221 x54 = rotateWordLeft(x54 + (x76 & ~x32) + (x10 & x32) + workingKey[i+2], 3); in encryptBlock()
222 x76 = rotateWordLeft(x76 + (x10 & ~x54) + (x32 & x54) + workingKey[i+3], 5); in encryptBlock()
225 x10 += workingKey[x76 & 63]; in encryptBlock()
226 x32 += workingKey[x10 & 63]; in encryptBlock()
232 x10 = rotateWordLeft(x10 + (x32 & ~x76) + (x54 & x76) + workingKey[i ], 1); in encryptBlock()
233 x32 = rotateWordLeft(x32 + (x54 & ~x10) + (x76 & x10) + workingKey[i+1], 2); in encryptBlock()
[all …]
|
| /external/libhevc/common/arm64/ |
| D | ihevc_intra_pred_luma_mode_18_34.s | 121 mov x10,x2
159 st1 {v0.8b},[x10],x3
160 st1 {v1.8b},[x10],x3
162 st1 {v2.8b},[x10],x3
165 st1 {v3.8b},[x10],x3
168 st1 {v4.8b},[x10],x3
170 st1 {v5.8b},[x10],x3
172 st1 {v6.8b},[x10],x3
174 st1 {v7.8b},[x10],x3
177 sub x20,x10,x14
[all …]
|
| D | ihevc_inter_pred_luma_copy.s | 103 add x10,x1,x3 //pu1_dst_tmp += dst_strd
107 st1 {v0.s}[0],[x10],x3 //vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
110 st1 {v0.s}[0],[x10],x3 //vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
113 st1 {v0.s}[0],[x10],x3 //vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
120 sub x1,x10,x15 //pu1_dst = pu1_dst_tmp
141 add x10,x1,x3 //pu1_dst_tmp += dst_strd
144 st1 {v1.8b},[x10],x3 //vst1_u8(pu1_dst_tmp, tmp_src)
147 st1 {v2.8b},[x10],x3 //vst1_u8(pu1_dst_tmp, tmp_src)
149 st1 {v3.8b},[x10],x3 //vst1_u8(pu1_dst_tmp, tmp_src)
155 sub x1,x10,x15 //pu1_dst = pu1_dst_tmp
[all …]
|
| D | ihevc_sao_edge_offset_class1.s | 85 ADD x10,x0,x9 //pu1_src[row * src_strd + wd - 1]
89 LDRB w14,[x10] //Load pu1_src[row * src_strd + wd - 1]
90 ADD x10,x10,x1
129 MOV x10,x0 //*pu1_src
144 ADD x10,x10,x1 //*pu1_src + src_strd
145 LD1 {v18.16b},[x10] //pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
146 ADD x6,x10,x1 //II Iteration *pu1_src + src_strd
152 SUB x10,x10,x1
209 ST1 { v20.16b},[x10],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
215 ST1 { v30.16b},[x10],x1 //II vst1q_u8(pu1_src_cpy, pu1_cur_row)
[all …]
|
| D | ihevc_intra_pred_luma_mode_27_to_33.s | 159 add x10,x8,x9 //(i row)*pu1_ref[ref_main_idx]
162 ld1 {v23.8b},[x10],x11 //(i row)ref_main_idx
166 ld1 {v9.8b},[x10] //(i row)ref_main_idx_1
171 add x10,x8,x9 //(iii)*pu1_ref[ref_main_idx]
188 ld1 {v16.8b},[x10],x11 //(iii)ref_main_idx
191 ld1 {v17.8b},[x10] //(iii)ref_main_idx_1
211 add x10,x8,x9 //(v)*pu1_ref[ref_main_idx]
213 ld1 {v23.8b},[x10],x11 //(v)ref_main_idx
220 ld1 {v9.8b},[x10] //(v)ref_main_idx_1
232 add x10,x8,x9 //(vii)*pu1_ref[ref_main_idx]
[all …]
|
| D | ihevc_intra_pred_chroma_mode_27_to_33.s | 154 add x10,x8,x9 //(i row)*pu1_ref[ref_main_idx]
157 ld1 {v23.8b},[x10],x11 //(i row)ref_main_idx
161 ld1 {v9.8b},[x10] //(i row)ref_main_idx_1
166 add x10,x8,x9 //(iii)*pu1_ref[ref_main_idx]
183 ld1 {v16.8b},[x10],x11 //(iii)ref_main_idx
186 ld1 {v17.8b},[x10] //(iii)ref_main_idx_1
206 add x10,x8,x9 //(v)*pu1_ref[ref_main_idx]
208 ld1 {v23.8b},[x10],x11 //(v)ref_main_idx
215 ld1 {v9.8b},[x10] //(v)ref_main_idx_1
227 add x10,x8,x9 //(vii)*pu1_ref[ref_main_idx]
[all …]
|
| D | ihevc_inter_pred_chroma_copy_w16out.s | 143 add x10,x1,x6
154 st1 {v22.1d},[x10],x6 //vst1q_lane_s64(pi2_dst_tmp, temp, 0)
157 st1 {v24.1d},[x10],x6 //vst1q_lane_s64(pi2_dst_tmp, temp, 0)
160 st1 {v26.1d},[x10],x6 //vst1q_lane_s64(pi2_dst_tmp, temp, 0)
166 sub x1,x10,x11,lsl #1
187 add x10,x1,x6
198 st1 {v22.1d},[x10],x6 //vst1q_lane_s64(pi2_dst_tmp, temp, 0)
221 add x10,x1,x5
258 st1 {v2.8h},[x10],x5 //vst1q_s16(pi2_dst_tmp, tmp)
261 st1 {v4.8h},[x10],x5 //vst1q_s16(pi2_dst_tmp, tmp)
[all …]
|
| D | ihevc_intra_pred_chroma_dc.s | 132 lsl x10,x4,#1 //2nt
135 subs x10, x10,#0x10
202 add x10, x8, x3
213 st2 {v16.8b, v17.8b}, [x10],#16
219 st2 {v16.8b, v17.8b}, [x10], x6
225 st2 {v16.8b, v17.8b}, [x10],#16
230 st2 {v16.8b, v17.8b}, [x10], x6
235 st2 {v16.8b, v17.8b}, [x10],#16
240 st2 {v16.8b, v17.8b}, [x10], x6
246 st2 {v16.8b, v17.8b}, [x10],x11
[all …]
|
| D | ihevc_inter_pred_luma_copy_w16out.s | 112 add x10,x1,x6
123 st1 {v22.d}[0],[x10],x6 //vst1q_lane_s64(pi2_dst_tmp, temp, 0)
126 st1 {v24.d}[0],[x10],x6 //vst1q_lane_s64(pi2_dst_tmp, temp, 0)
129 st1 {v26.d}[0],[x10],x6 //vst1q_lane_s64(pi2_dst_tmp, temp, 0)
135 sub x1,x10,x11,lsl #1
161 add x10,x1,x5
198 st1 {v2.8h},[x10],x5 //vst1q_s16(pi2_dst_tmp, tmp)
201 st1 {v4.8h},[x10],x5 //vst1q_s16(pi2_dst_tmp, tmp)
204 st1 {v6.8h},[x10],x5 //vst1q_s16(pi2_dst_tmp, tmp)
225 add x10,x1,x5
[all …]
|
| D | ihevc_sao_edge_offset_class1_chroma.s | 92 mov x24,x10 // wd 64
102 SUB x10,x8,#2 //wd - 2
103 LDRH w11,[x3,x10] //pu1_src_top[wd - 2]
105 ADD x11,x0,x10 //pu1_src[row * src_strd + wd - 2]
150 MOV x10,x0 //*pu1_src
168 ADD x10,x10,x1 //*pu1_src + src_strd
169 LD1 {v18.16b},[x10] //pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
172 ADD x6,x10,x1 //II Iteration *pu1_src + src_strd
181 SUB x10,x10,x1
257 ST1 { v20.16b},[x10],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
[all …]
|
| D | ihevc_intra_pred_chroma_ver.s | 120 add x10, x8, x3
130 st2 {v20.8b, v21.8b}, [x10],#16
135 st2 {v22.8b, v23.8b}, [x10], x11
143 st2 {v20.8b, v21.8b}, [x10],#16
148 st2 {v22.8b, v23.8b}, [x10], x11
156 st2 {v20.8b, v21.8b}, [x10],#16
161 st2 {v22.8b, v23.8b}, [x10], x11
168 st2 {v20.8b, v21.8b}, [x10],#16
173 st2 {v22.8b, v23.8b}, [x10], x11
189 add x10, x8, x3
[all …]
|
| D | ihevc_deblk_luma_horz.s | 123 and x10,x10,#0xff
141 subs x8,x8,x10,lsl #1
171 subs x11,x2,x10,lsl #1
204 asr x10,x5,#2
206 cmp x10,x3,lsl #1
209 add x10,x1,x1,lsl #1
221 ldr w8, [x0,x10] // has the 3 value
242 mov x10,#5
244 mul x10, x10, x6
246 add x10, x10,#1
[all …]
|
| D | ihevc_intra_pred_filters_luma_mode_19_to_25.s | 271 add x10,x8,x9 //(i row)*pu1_ref[ref_main_idx]
273 ld1 {v23.8b},[x10],x11 //(i row)ref_main_idx
276 ld1 {v9.8b},[x10] //(i row)ref_main_idx_1
281 add x10,x8,x9 //(iii)*pu1_ref[ref_main_idx]
297 ld1 {v16.8b},[x10],x11 //(iii)ref_main_idx
300 ld1 {v17.8b},[x10] //(iii)ref_main_idx_1
320 add x10,x8,x9 //(v)*pu1_ref[ref_main_idx]
322 ld1 {v23.8b},[x10],x11 //(v)ref_main_idx
328 ld1 {v9.8b},[x10] //(v)ref_main_idx_1
339 add x10,x8,x9 //(vii)*pu1_ref[ref_main_idx]
[all …]
|
| D | ihevc_intra_pred_chroma_mode_18_34.s | 120 mov x10,x2
137 st1 {v0.8b, v1.8b},[x10],x3
139 st1 {v2.8b, v3.8b},[x10],x3
141 st1 {v4.8b, v5.8b},[x10],x3
143 st1 {v6.8b, v7.8b},[x10],x3
145 st1 {v16.8b, v17.8b},[x10],x3
147 st1 {v18.8b, v19.8b},[x10],x3
149 st1 {v20.8b, v21.8b},[x10],x3
151 st1 {v22.8b, v23.8b},[x10],x3
158 add x10,x2,#16
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | unpredictable-AI1cmp-arm.txt | 4 # CHECK: 0x01 0x10 0x50 0x03
5 0x01 0x10 0x50 0x03
8 # CHECK: 0x82 0x10 0x50 0x01
9 0x82 0x10 0x50 0x01
12 # CHECK: 0x02 0x10 0x50 0x01
13 0x02 0x10 0x50 0x01
20 # CHECK: 0x10 0x11 0x52 0x01
21 0x10 0x11 0x52 0x01
24 # CHECK: 0x10 0x0f 0x51 0x01
25 0x10 0x0f 0x51 0x01
[all …]
|
| D | invalid-armv8.txt | 38 [0x10 0x01 0x00 0xee]
41 # CHECK-NEXT: [0x10 0x01 0x00 0xee]
43 [0x10 0x01 0x00 0xfe]
46 # CHECK-NEXT: [0x10 0x01 0x00 0xfe]
48 [0x10 0x0e 0x00 0xfe]
51 # CHECK-NEXT: [0x10 0x0e 0x00 0xfe]
53 [0x10 0x0f 0x00 0xfe]
56 # CHECK-NEXT: [0x10 0x0f 0x00 0xfe]
58 [0x10 0x01 0x10 0xee]
61 # CHECK-NEXT: [0x10 0x01 0x10 0xee]
[all …]
|
| D | invalid-thumbv8.txt | 38 [0x00 0xee 0x10 0x01]
41 # CHECK-NEXT: [0x00 0xee 0x10 0x01]
43 [0x00 0xfe 0x10 0x01]
46 # CHECK-NEXT: [0x00 0xfe 0x10 0x01]
48 [0x00 0xfe 0x10 0x0e]
51 # CHECK-NEXT: [0x00 0xfe 0x10 0x0e]
53 [0x00 0xfe 0x10 0x0f]
56 # CHECK-NEXT: [0x00 0xfe 0x10 0x0f]
58 [0x10 0xee 0x10 0x01]
61 # CHECK-NEXT: [0x10 0xee 0x10 0x01]
[all …]
|
| D | addrmode2-reencoding.txt | 3 0x00 0x10 0xb0 0xe4
4 0x00 0x10 0xf0 0xe4
5 0x00 0x10 0xa0 0xe4
6 0x00 0x10 0xe0 0xe4
8 # CHECK: ldrt r1, [r0], #0 @ encoding: [0x00,0x10,0xb0,0xe4]
9 # CHECK: ldrbt r1, [r0], #0 @ encoding: [0x00,0x10,0xf0,0xe4]
10 # CHECK: strt r1, [r0], #0 @ encoding: [0x00,0x10,0xa0,0xe4]
11 # CHECK: strbt r1, [r0], #0 @ encoding: [0x00,0x10,0xe0,0xe4]
|
| D | unpredictable-swp-arm.txt | 4 # CHECK: 0x9f 0x10 0x03 0x01
5 0x9f 0x10 0x03 0x01
16 # CHECK: 0x90 0x10 0x0f 0x01
17 0x90 0x10 0x0f 0x01
20 # CHECK: 0x90 0x10 0x01 0x01
21 0x90 0x10 0x01 0x01
24 # CHECK: 0x90 0x10 0x00 0x01
25 0x90 0x10 0x00 0x01
|
| /external/boringssl/linux-aarch64/crypto/bn/ |
| D | armv8-mont.S | 30 mul x10,x8,x9 // ap[1]*bp[0]
56 adds x6,x10,x7
62 mul x10,x8,x9 // ap[j]*bp[0]
74 adds x6,x10,x7
99 mul x10,x8,x9 // ap[1]*bp[i]
119 adds x6,x10,x7
127 mul x10,x8,x9 // ap[j]*bp[i]
141 adds x6,x10,x7
224 ldp x10,x11,[x1,#8*4]
296 mul x17,x10,x6
[all …]
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r6/ |
| D | valid-mips64r6-el.txt | 88 0x9e 0x10 0x64 0x00 # CHECK: ddiv $2, $3, $4
89 0x9f 0x10 0x64 0x00 # CHECK: ddivu $2, $3, $4
92 0x9a 0x10 0x64 0x00 # CHECK: div $2, $3, $4
93 0x9b 0x10 0x64 0x00 # CHECK: divu $2, $3, $4
94 0xd5 0x10 0x64 0x00 # CHECK: dlsa $2, $3, $4, 4
96 0xde 0x10 0x64 0x00 # CHECK: dmod $2, $3, $4
97 0xdf 0x10 0x64 0x00 # CHECK: dmodu $2, $3, $4
99 0xdc 0x10 0x64 0x00 # CHECK: dmuh $2, $3, $4
100 0xdd 0x10 0x64 0x00 # CHECK: dmuhu $2, $3, $4
101 0x9c 0x10 0x64 0x00 # CHECK: dmul $2, $3, $4
[all …]
|
| D | valid-mips64r6.txt | 8 0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
9 0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
11 0x00 0x64 0x10 0x35 # CHECK: seleqz $2, $3, $4
12 0x00 0x64 0x10 0x37 # CHECK: selnez $2, $3, $4
13 0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4
14 0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4
15 0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4
16 0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4
17 0x00 0x64 0x10 0x9c # CHECK: dmul $2, $3, $4
18 0x00 0x64 0x10 0x9d # CHECK: dmulu $2, $3, $4
[all …]
|