A_DISP_REG_N (reference) in projects: toolchain

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Searched refs:A_DISP_REG_N (Results 1 – 25 of 43) sorted by relevance

/toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/arch/
D	sh2a-nofpu.s	18 …0dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) / {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,R… 22 …0dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) / {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,R… 26 …1dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) / {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,R… 30 …00dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) / {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 32 …0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) / {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 34 …01dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) / {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 36 …0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) / {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 57 …00dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) / {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 58 …dddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) / {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 59 …dddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) / {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… [all …]
D	sh2a.s	15 …ddddddd fmov.d <DX_REG_M>,@(<DISP12>,<REG_N>) / {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,R… 17 …ddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) / {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,R… 89 …0dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) / {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,R… 91 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R… 105 …0dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) / {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,R… 120 …1dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) / {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,R… 253 …00dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) / {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 255 …0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) / {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 257 …01dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) / {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 259 …0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */ {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… [all …]
D	sh.s	`72 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
D	sh2.s	`85 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
D	sh2a-nofpu-or-sh3-nommu.s	`80 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
D	sh2a-nofpu-or-sh4-nommu-nofpu.s	`79 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
D	sh3.s	`85 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
D	sh3-nommu.s	`90 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
D	sh4-nommu-nofpu.s	`96 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
D	sh4-nofpu.s	`89 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
D	sh4a-nofpu.s	`96 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-sh/arch/
D	sh2a-nofpu.s	18 …0dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) / {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,R… 22 …0dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) / {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,R… 26 …1dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) / {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,R… 30 …00dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) / {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 32 …0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) / {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 34 …01dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) / {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 36 …0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) / {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 57 …00dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) / {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 58 …dddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) / {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 59 …dddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) / {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… [all …]
D	sh2a.s	15 …ddddddd fmov.d <DX_REG_M>,@(<DISP12>,<REG_N>) / {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,R… 17 …ddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) / {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,R… 89 …0dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) / {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,R… 91 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R… 105 …0dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) / {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,R… 120 …1dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) / {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,R… 253 …00dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) / {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 255 …0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) / {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 257 …01dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) / {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… 259 …0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */ {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,I… [all …]
D	sh.s	`72 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
D	sh2.s	`85 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
D	sh2a-nofpu-or-sh3-nommu.s	`80 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
D	sh2a-nofpu-or-sh4-nommu-nofpu.s	`79 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
D	sh3.s	`85 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
D	sh3-nommu.s	`90 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
D	sh4-nommu-nofpu.s	`96 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
D	sh4-nofpu.s	`89 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
D	sh2a-or-sh3e.s	`83 … 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,R…`
/toolchain/binutils/binutils-2.25/opcodes/
D	sh-opc.h	110 A_DISP_REG_N, enumerator 588 {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up \| arch… 591 /* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,… 616 {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up \| a… 644 {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up \| a… 1094 {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up \| arch_… 1110 {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up \| arch_o… 1145 {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up \| ar… 1148 {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up \| arc… 1151 {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up \| ar… [all …]
D	sh-dis.c	`710 case A_DISP_REG_N: in print_insn_sh()`
/toolchain/binutils/binutils-2.25/gas/config/
D	tc-sh.c	`1491 op->type = A_DISP_REG_N; in parse_at() 1738 case A_DISP_REG_N: in get_specific() 2197 \|\| arg == A_DISP_REG_N)) in get_specific()`

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