| /toolchain/binutils/binutils-2.25/opcodes/ |
| D | rl78-decode.opc | 111 #define DM(r,a) OP (0, RL78_Operand_Indirect, RL78_Reg_##r, a)
227 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
259 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
311 ID(and); DM(None, SADDR); SC(IMMU(1)); Fz;
432 ID(call); DM(None, 0x80 + mm*16 + nnn*2);
437 ID(mov); DM(None, IMMU(2)); DB(bit); SC(0);
440 ID(mov); DM(HL, 0); DB(bit); SC(0);
450 ID(mov); DM(None, op0); DB(bit); SC(0);
455 ID(mov); DM(None, SADDR); DB(bit); SC(0);
460 ID(mov); DM(None, IMMU(2)); SC(0);
[all …]
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| D | rl78-decode.c | 112 #define DM(r,a) OP (0, RL78_Operand_Indirect, RL78_Reg_##r, a) macro
319 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac; in rl78_decode_opcode()
488 ID(mov); DM(B, IMMU(2)); SR(A); in rl78_decode_opcode()
503 ID(mov); DM(B, IMMU(2)); SC(IMMU(1)); in rl78_decode_opcode()
518 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac; in rl78_decode_opcode()
693 ID(mov); DM(C, IMMU(2)); SR(A); in rl78_decode_opcode()
723 ID(sub); DM(None, SADDR); SC(IMMU(1)); Fzac; in rl78_decode_opcode()
1259 ID(mov); DM(C, IMMU(2)); SC(IMMU(1)); in rl78_decode_opcode()
1274 ID(mov); DM(BC, IMMU(2)); SC(IMMU(1)); in rl78_decode_opcode()
1289 ID(subc); DM(None, SADDR); SC(IMMU(1)); Fzac; in rl78_decode_opcode()
[all …]
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| D | msp430-decode.opc | 80 #define DM(r, a) OP (0, MSP430_Operand_Indirect, r, a)
180 DM (reg, x);
463 ID (MSO_mov); SR (srcr); DM (dstr, IMMS(2));
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| D | msp430-decode.c | 81 #define DM(r, a) OP (0, MSP430_Operand_Indirect, r, a) macro
181 DM (reg, x); in encode_ad()
525 ID (MSO_mov); SR (srcr); DM (dstr, IMMS(2)); in msp430_decode_opcode()
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| D | ChangeLog-2008 | 365 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
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| D | ppc-opc.c | 853 #define DM XC6 + 1 macro
854 #define SHW DM
858 #define DMEX DM + 1
6032 {"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, DM}},
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| D | ChangeLog-9297 | 1422 * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/metag/ |
| D | metadsp21.s | 5 DM ADD D0Re0,D0Re0,A1.7
12 DM ADD D0Re0,D0Re0,AC0.0
14 DM ADD D0Re0,D0Re0,[D0AR.0++]
16 DM ADD D0Re0,D0Re0,[D0AR.0+D0ARI.0++]
23 DM ADD D0Re0,D0.7,[D0AR.0]
33 DM ADD D0Re0,[D0AR.0],RD
116 DM ADD D0.7,D0Re0,[D0AR.0]
141 DM ADD D0.7,D0.7,D0.7
168 DM ADD D0.7,[D0AR.0],D0.7
205 DM ADD D0.7,[D0AR.0+D0ARI.0++],AC0.0
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| D | metadsp21.d | 13 .*: 00000f09 DM ADD D0Re0,D0Re0,A1\.7
20 .*: 00002188 DM ADD D0Re0,D0Re0,AC0\.0
22 .*: 00002308 DM ADD D0Re0,D0Re0,\[D0AR\.0\+\+\]
24 .*: 00002508 DM ADD D0Re0,D0Re0,\[D0AR\.0\+D0ARI\.0\+\+\]
31 .*: 0001e108 DM ADD D0Re0,D0\.7,\[D0AR\.0\]
41 .*: 00042109 DM ADD D0Re0,\[D0AR\.0\],RD
124 .*: 00382108 DM ADD D0\.7,D0Re0,\[D0AR\.0\]
149 .*: 0039cf08 DM ADD D0\.7,D0\.7,D0\.7
176 .*: 003c0f08 DM ADD D0\.7,\[D0AR\.0\],D0\.7
213 .*: 003ca188 DM ADD D0\.7,\[D0AR\.0\+D0ARI\.0\+\+\],AC0\.0
[all …]
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| D | arm7dm.d | 1 # name: ARM 7DM instructions
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| /toolchain/binutils/binutils-2.25/cpu/ |
| D | mep-core.cpu | 2302 ; set DBG.DM.
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| /toolchain/binutils/binutils-2.25/gas/ |
| D | ChangeLog-9295 | 2680 (ARM_{1,2,250,3,6,7,7DM,ANY,2UP,ALL,3UP,6UP,LONGMUL}): Define processor
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