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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/
Dexpected_comparison_errors.s16 CC = I0 == 0;
17 CC = I0 == I0;
18 CC = I0 < 0;
19 CC = I0 < I0;
20 CC = I0 <= 0;
21 CC = I0 <= I0;
Dexpected_errors.s58 [ I0 ++ R2 ] = R2;
62 [ I0 ++ P2 ] = R2;
65 W [ I0 ++ R2 ] = R2.h;
69 W [ I0 ++ P2 ] = R2.h;
72 [ I0 ++ ] = P2;
75 W [ I0 ++ ] = P2.h;
78 W [ I0 ++ ] = R2;
82 B [ I0 ++ ] = R2;
86 R2 = [ I0 ++ R2 ];
90 R2 = [ I0 ++ P2 ];
[all …]
Dparallel.d8 0: 0a ce 13 8a R5 = DEPOSIT \(R3, R2\) \|\| I0 \+= 0x2 \|\| NOP;
18 28: 0a ce 0e 4a R5 = EXTRACT \(R6, R1.L\) \(X\) \|\| I0 -= 0x2 \|\| NOP;
22 38: 08 ce 13 00 BITMUX \(R2, R3, A0\) \(ASR\) \|\| I0 \+= 0x2 \|\| NOP;
32 60: 10 cc 3f 00 A0 = ABS A0 \|\| P2 = \[SP \+ 0x3c\] \|\| R0 = \[I0\];
40 80: 10 cc 3f c0 A1 = ABS A1, A0 = ABS A0 \|\| R4 = \[P5 \+ 0x38\] \|\| R0.H = W\[I0\];
52 b0: 25 cc 28 96 R3.H = R5 \+ R0 \(RND20\) \|\| R0 = B\[P0\] \(X\) \|\| \[I0\] = R6;
66 e8: 07 ce 08 ca R5.L = EXPADJ \(R0.H, R1.L\) \|\| R1 = B\[P4\] \(Z\) \|\| W\[I0\] = R2.L;
68 f0: 07 ce 2b 48 R4.L = EXPADJ \(R3, R5.L\) \(V\) \|\| R1 = B\[P5\] \(Z\) \|\| W\[I0\+\+\] = R1.L;
90 148: 2b cc 3f 40 R0.H = \(A0 \+= A1\) \|\| B\[P0\] = R3 \|\| R7 = \[I0\+\+\];
92 150: 00 ca 0a 24 R0.L = R1.H \* R2.L \|\| B\[P1\] = R3 \|\| R1 = \[I0\+\+\];
[all …]
Dloop_temps.s205 I0 = P0; define
232 I0 = B0; define
235 R4 = [I0++] || R5 = [I2--];
238 A1 -= R4.H*R5.H, A0 += R4.L*R5.L (IS) || R4 = [I0++] || R5 = [I2--];
252 I0 = B0; define
258 R4 = [I0++];
271 A1 -= R4.H*R5.H, A0 += R4.L*R5.L (IS) || R4 = [I0++] || R5 = [I2--];
290 I0 = P0; define
294 R5 = [I2--] || R4 = [I0++];
297 A1 -= R4.H*R5.H, A0 += R4.L*R5.L (IS) || R4 = [I0++] || R5 = [I2--];
Dresource_conflict.s10 R0 = (A0 += A1) || R0.L = W [I0++];
11 R0 = (A0 += A1) || R0.H = W [I0++];
12 R0.h = (A0 += A1) || R0.H = W [I0++];
13 R0.l = (A0 += A1) || R0.L = W [I0++];
Dparallel.s2 R5 = Deposit (r3, r2) || I0 += 2;
11 Bitmux (r2, R3, a0) (aSr) || I0 += 2;
23 A1 = abs a1, a0 = ABS A0 || R4=[p5+56] || r0.h = w [I0];
42 R4.L = expadj (R3, R5.L) (V) || r1 = b [p5] (z) || W [I0++] = R1.L;
69 r3.H = r5.H * r0.L || r4 = b [p0] (x) || [I0++M0] = R0;
116 r3 = (A1 -= r0.l * R0.H) || w [p0] = r2.L || r7.L = w[I0++];
141 R1 = [I0++] || R2 = ABS R2 || NOP;
146 R4.L = A0.x || R4.H = W[I1++] || W[I0] = R4.H ;
147 R4.L = A0.x || W[I1++] = R4.L || R4.H = W[I0--] ;
149 A0 += A1 (W32) || R3.L = W[I0] || R0 = [I0++ M3] ;
[all …]
Dstore.d25 26: 01 9f \[I0\] = R1;
32 30: 40 9e W\[I0\+\+\] = R0.H;
38 38: 20 9f W\[I0\] = R0.L;
Dparallel4.d8 0: 0d ce 15 0e R7 = ALIGN8 \(R5, R2\) \|\| \[I0\] = R0 \|\| NOP;
10 8: 0d ce 08 4a R5 = ALIGN16 \(R0, R1\) \|\| \[I0\+\+\] = R0 \|\| NOP;
12 10: 0d ce 05 84 R2 = ALIGN24 \(R5, R0\) \|\| \[I0--\] = R0 \|\| NOP;
Dstore.s34 W[I0++] = r0.h;
42 W [I0] = r0.l;
Dstack2.s17 [--SP ] = I0;
74 I0= [ SP ++ ] ;
Dmove2.s74 R0 = I0;
92 P0 = I0;
111 A0.X = I0;
132 I0 = R0; define
136 I0 = A0.X; define
171 I0 = I1; define
Dstack2.d12 8: 50 01 \[--SP\] = I0;
48 50: 10 01 I0 = \[SP\+\+\];
Dparallel2.d30 58: 09 cc 10 c0 A1.X = R2.L \|\| R0 = \[I0 \+\+ M0\] \|\| NOP;
32 60: 0a cc 3f 00 R0.L = A0.X \|\| R1 = \[I0 \+\+ M1\] \|\| NOP;
34 68: 0a cc 3f 4e R7.L = A1.X \|\| R0 = \[I0 \+\+ M2\] \|\| NOP;
36 70: 09 cc 18 00 A0.L = R3.L \|\| R0 = \[I0 \+\+ M3\] \|\| NOP;
Dmove2.d60 68: 80 30 R0 = I0;
76 88: 80 32 P0 = I0;
92 a8: 80 38 A0.X = I0;
108 c8: 00 34 I0 = R0;
112 d0: 00 35 I0 = A0.X;
140 108: 81 34 I0 = I1;
Dexpected_move_errors.s7 LC1 = I0;
Dload.d59 96: 02 9d R2 = \[I0\];
83 c2: 40 9d R0.H = W\[I0\];
Dstack.d24 1a: 10 01 I0 = \[SP\+\+\];
Darithmetic.d40 52: 60 9f I0 \+= 0x2;.*
79 9e: e0 9e I0 \+= M0 \(BREV\);
180 1ce: 6c 9f I0 -= 0x4;.*
Dvector2.d452 6f0: 12 cc 02 00 SAA \(R1:0, R3:2\) \|\| R0 = \[I0\+\+\] \|\| R2 = \[I1\+\+\];
454 6f8: 12 cc 02 20 SAA \(R1:0, R3:2\) \(R\) \|\| R1 = \[I0\+\+\] \|\| R3 = \[I1\+\+\];
456 700: 03 c8 00 18 MNOP \|\| R1 = \[I0\+\+\] \|\| R3 = \[I1\+\+\];
458 …3 0e R7.H = R7.L = SIGN \(R2.H\) \* R3.H \+ SIGN \(R2.L\) \* R3.L \|\| I0 \+= M3 \|\| R0 = \[I0\];
460 …: 01 cc 94 88 R2 = R2 \+\|\+ R4, R4 = R2 -\|- R4 \(ASR\) \|\| I0 \+= M0 \(BREV\) \|\| R1 = \[I0\];
466 ….H = \(A1 \+= R0.L \* R1.H\), R3.L = \(A0 \+= R0.L \* R1.L\) \|\| R0 = \[P0\+\+\] \|\| R1 = \[I0\];
468 730: 04 ce 01 c2 R1 = PACK \(R1.H, R0.H\) \|\| \[I0\+\+\] = R0 \|\| R2.L = W\[I2\+\+\];
Dpseudo.s23 DBG I0;
Dexpected_comparison_errors.l18 .*:17: Error: Bad register in comparison. Input text was I0.
Dparallel3.d120 …1c0: 05 c9 1a e0 R0.H = \(A1 \+= R3.H \* R2.H\), R0.L = \(A0 = R3.L \* R2.L\) \(IS\) \|\| \[I0\] …
122 …1c8: 1c c8 b7 d0 R3 = \(A1 = R6.H \* R7.H\) \(M\), A0 -= R6.L \* R7.L \|\| \[I0\+\+\] = R1 \|\| N…
124 …1d0: 1c c8 3c 2e R1 = \(A1 = R7.L \* R4.L\) \(M\), R0 = \(A0 \+= R7.H \* R4.H\) \|\| \[I0--\] = R…
Dallinsn16.d280 [^:]+: 10 01 + I0 = \[SP\+\+\];
344 [^:]+: 50 01 + \[--SP\] = I0;
12424 [^:]+: 80 30 + R0 = I0;
12432 [^:]+: 88 30 + R1 = I0;
12440 [^:]+: 90 30 + R2 = I0;
12448 [^:]+: 98 30 + R3 = I0;
12456 [^:]+: a0 30 + R4 = I0;
12464 [^:]+: a8 30 + R5 = I0;
12472 [^:]+: b0 30 + R6 = I0;
12480 [^:]+: b8 30 + R7 = I0;
[all …]
/toolchain/binutils/binutils-2.25/cpu/
Dfrv.opc282 /* I0 */ UNIT_I0,
287 /* IALL */ UNIT_I01, /* only I0 and I1 units */
299 /* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */
300 /* IACC */ UNIT_I01, /* iacc multiply in I0 or I1 unit. */
301 /* LOAD */ UNIT_I0, /* load only in I0 unit. */
302 /* STORE */ UNIT_I0, /* store only in I0 unit. */
303 /* SCAN */ UNIT_I0, /* scan only in I0 unit. */
317 /* I0 */ UNIT_I0,
322 /* IALL */ UNIT_I01, /* only I0 and I1 units */
334 /* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */
[all …]
/toolchain/binutils/binutils-2.25/opcodes/
Dia64-opc-i.c24 #define I0 IA64_TYPE_I, 0 macro
113 {"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX, 0, NULL},
114 {"nop.i", I0, OpX3X6Yb (0, 0, 0x01, 0), {IMMU21}, X_IN_MLX, 0, NULL},
115 {"hint.i", I0, OpX3X6Yb (0, 0, 0x01, 1), {IMMU21}, X_IN_MLX, 0, NULL},
116 {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}, EMPTY},
288 #undef I0

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