| /toolchain/binutils/binutils-2.25/opcodes/ |
| D | aarch64-tbl.h | 29 #define OP2(a,b) {OPND(a), OPND(b)} macro
1239 {"ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF},
1241 {"ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF},
1245 …{"cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_S…
1248 …{"cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_S…
1251 {"mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, CORE, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF},
1253 {"cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF},
1256 {"cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF},
1260 …{"cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF…
1262 …{"neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF…
[all …]
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| D | cr16-opc.c | 138 #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ argument
140 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
142 {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\
144 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
150 #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ argument
152 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
154 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
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| /toolchain/binutils/binutils-2.25/include/opcode/ |
| D | h8300.h | 546 #define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ argument
554 …{CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, …
558 …{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1, 6, OP2, 10, …
559 …{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2, 6, OP2, 10, …
560 …{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3, 6, OP2, 10, …
561 …{CODE, AV_H8, 4, NAME, {{SRC, ABS16DST, E}}, {{ 6, OP2, 8, …
562 …{CODE, AV_H8, 6, NAME, {{SRC, ABS32DST, E}}, {{ 6, OP2, 10, …
564 #define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ argument
572 …{CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, …
576 …{CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{7, 8, B30 | DISPREG, 1, 6, OP2, 2, …
[all …]
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| D | tic6x-opcode-table.h | 43 #define OP2(a, b) 2, { a, b } macro
134 OP2(ORXREG1, OWREG1),
139 OP2(ORREGL1, OWREGL1),
144 OP2(ORXREG1, OWREG1),
150 OP2(ORREGD1, OWREGD12),
156 OP2(ORXREG1, OWREG1),
355 OP2(OLCST, OWREG1),
361 OP2(OACST, OWREG1),
513 OP2(OLCST, ORWREG1),
518 OP2(ORXREG1, OWREG2),
[all …]
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| D | sparc.h | 251 #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ macro
260 #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
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| /toolchain/binutils/binutils-2.25/gas/config/ |
| D | tc-rx.c | 2219 #define OP2(x) op[target_big_endian ? 1-x : x] in md_apply_fix() macro
2253 OP2(1) = val & 0xff; in md_apply_fix()
2254 OP2(0) = (val >> 8) & 0xff; in md_apply_fix()
2296 OP2(0) = val & 0xff; in md_apply_fix()
2297 OP2(1) = (val >> 8) & 0xff; in md_apply_fix()
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| /toolchain/binutils/binutils-2.25/bfd/ |
| D | ChangeLog-0203 | 3836 PLT,OP0,OP1,OP2,ASM_EXPAND,ASM_SIMPLIFY}.
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