Searched refs:POSTINC (Results 1 – 7 of 7) sorted by relevance
/toolchain/binutils/binutils-2.25/opcodes/ |
D | ia64-opc.h | 43 #define POSTINC IA64_OPCODE_POSTINC macro
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D | h8300-dis.c | 236 else if ((x & MODE) == POSTINC) in print_one_arg() 474 || (looking_for & MODE) == POSTINC in bfd_h8_disassemble()
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D | ia64-opc-m.c | 781 #define LDINCREG(c,h) M, OpMXX6aHint (4, 1, 0, c, h), {R1, MR3, R2}, POSTINC, 0, NULL 1147 #define LDINCIMMED(c,h) M, OpX6aHint (5, c, h), {R1, MR3, IMM9b}, POSTINC, 0, NULL 1262 #define STINCIMMED(c,h) M, OpX6aHint (5, c, h), {MR3, R2, IMM9a}, POSTINC, 0, NULL 1642 #define FLDINCREG(c,h) M, OpMXX6aHint (6, 1, 0, c, h), {F1, MR3, R2}, POSTINC, 0, NULL 1850 #define LD(a,b,c) M2, OpMXX6aHint (6, 1, 1, a, b), {F1, F2, MR3, c}, POSTINC, 0, NULL 1981 #define LFETCHINCREG(x6,hnt,h) M0, OpMXX6aHintHlf (6, 1, 0, x6, hnt, h), {MR3, R2}, POSTINC, 0, NULL 1982 #define LFETCHINCREG_SYN(x6,hnt,h) M0, OpMXX6aHintHlf (6, 1, 0, x6, hnt, h), {MR3, R2}, POSTINC|PSE… 2043 #define FLDINCIMMED(c,h) M, OpX6aHint (7, c, h), {F1, MR3, IMM9b}, POSTINC, 0, NULL 2122 #define FSTINCIMMED(c,h) M, OpX6aHint (7, c, h), {MR3, F2, IMM9a}, POSTINC, 0, NULL 2138 #define LFETCHINCIMMED(x6,hnt,h) M0, OpX6aHintHlf (7, x6, hnt, h), {MR3, IMM9b}, POSTINC, 0, NULL [all …]
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D | ChangeLog-0001 | 1560 * ia64-opc-m.c: Add POSTINC to all instructions with postincrement 1562 * ia64-opc.h (POSTINC): Define.
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/toolchain/binutils/binutils-2.25/include/opcode/ |
D | h8300.h | 53 POSTINC = 0x0700, enumerator 75 INC = POSTINC, 201 RSPOSTINC = SRC | POSTINC, 202 RDPOSTINC = DST | POSTINC,
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/toolchain/binutils/binutils-2.25/gas/config/ |
D | tc-h8300.c | 1509 || c2 == POSTINC || c2 == POSTDEC) in build_bytes()
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/toolchain/binutils/binutils-2.25/cpu/ |
D | epiphany.cpu | 372 (define-normal-insn-enum post-index "+/- index register" () DIR_ f-addsubx (POSTINC POSTDEC))
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