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/toolchain/binutils/binutils-2.25/opcodes/
DMakefile.am201 msp430-decode.c \
224 rl78-decode.c \
226 rx-decode.c \
518 $(srcdir)/msp430-decode.c \
519 $(srcdir)/rl78-decode.c \
520 $(srcdir)/rx-decode.c
572 $(srcdir)/msp430-decode.c: @MAINT@ $(srcdir)/msp430-decode.opc opc2c$(EXEEXT_FOR_BUILD)
573 ./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/msp430-decode.opc > $(srcdir)/msp430-decode.c
575 $(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD)
576 ./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c
[all …]
DMakefile.in474 msp430-decode.c \
497 rl78-decode.c \
499 rx-decode.c \
644 $(srcdir)/msp430-decode.c \
645 $(srcdir)/rl78-decode.c \
646 $(srcdir)/rx-decode.c
874 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/msp430-decode.Plo@am__quote@
897 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rl78-decode.Plo@am__quote@
899 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rx-decode.Plo@am__quote@
1434 $(srcdir)/msp430-decode.c: @MAINT@ $(srcdir)/msp430-decode.opc opc2c$(EXEEXT_FOR_BUILD)
[all …]
DChangeLog-20128 * rl78-decode.c: Likewise.
9 * rl78-decode.opc: Likewise.
10 * rx-decode.c: Likewise.
11 * rx-decode.opc: Likewise.
401 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
404 * rl78-decode.c: Regenerate.
534 * rl78-decode.c: Regenerate.
683 * rx-decode.c: Regenerate.
744 * rl78-decode.opc: Likewise.
745 * rl78-decode.c: Regenerate.
[all …]
DChangeLog-2013874 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
876 * rx-decode.c: Regenerate.
892 * msp430-decode.opc: New.
893 * msp430-decode.c: New/generated.
894 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
896 Add rule to build msp430-decode.c frommsp430decode.opc
899 * configure.in: Add msp430-decode.lo to msp430 architecture files.
931 * rx-decode.opc (rx_decode_opcode): Bit operations on
933 * rx-decode.c: Regenerate.
1159 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
[all …]
DChangeLog-201169 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and
71 (MAINTAINERCLEANFILES): Add rl78-decode.c.
72 (rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
78 * rl78-decode.c: New file.
79 * rl78-decode.opc: New file.
579 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
580 * rx-decode.c: Regenerate.
Dconfigure.ac300 bfd_msp430_arch) ta="$ta msp430-dis.lo msp430-decode.lo" ;;
312 bfd_rl78_arch) ta="$ta rl78-dis.lo rl78-decode.lo";;
313 bfd_rx_arch) ta="$ta rx-dis.lo rx-decode.lo";;
DChangeLog-2009486 * rx-decode.opc (rx_decode_opcode) (mvtipl): Add.
488 * rx-decode.c: Regenerate.
538 * rx-decode.opc (decode_opcode): Fix flags for MUL, SUNTIL, and SWHILE.
539 * rx-decode.c: Regenerated.
614 ($(srcdir)/rx-decode.c): Use @MAINT@. Use $(EXEEXT_FOR_BUILD)
619 (MAINTAINERCLEANFILES): Add $(srcdir)/rx-decode.c.
621 * rx-decode.c: Regenerated.
656 * rx-decode.c: New file.
657 * rx-decode.opc: New file.
DChangeLog-2010364 * rx-decode.opc (SRR): New.
367 * rx-decode.c: Regenerate.
375 * rx-decode.opc (store_flags): Remove, replace with F_* macros.
377 * rx-decode.c: Regenerate.
DChangeLog732 * rx-decode.opc (bwl): Allow for bogus instructions with a size
735 * rx-decode.c: Regenerate.
760 * msp430-decode.c: Regenerate.
DChangeLog-2004464 determine decode size of insns.
629 that reserved instruction 0xfffd does not decode the same
Dmsp430-decode.opc28 #include "opcode/msp430-decode.h"
DChangeLog-20071462 (arm_decode_shift): New parameter, print_shift. Only decode the
1464 (print_insn_arm): Support for operand type q with no shift decode.
/toolchain/binutils/binutils-2.25/cpu/
Dsimplify.inc44 ; Normally, fields are unsigned and have no encode/decode needs.
53 (define-pmacro (df name comment attrs start length mode encode decode)
54 "Shorthand form of normal fields requiring mode, encode/decode."
55 (define-full-ifield name comment attrs start length mode encode decode)
78 ; default encode/decode support.
Dm32r.cpu103 ; Initial bitnumbers to decode insns by.
104 (decode-assist (0 1 2 3 8 9 10 11))
111 (0 1 2 7 8 9 10) ; decode-assist
231 (pipeline p-non-mem "" () ((fetch) (decode) (execute) (writeback)))
232 (pipeline p-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
289 (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
302 (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
303 (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
304 (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
355 (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
[all …]
Depiphany.opc57 /* Can only depend on instruction having 4 decode bits which gets us to the
Dxstormy16.cpu341 (decode (value pc) (add HI value #x7F00))
360 (decode (value pc) (add SI value (add SI pc 2)))
372 (decode (value pc) (add SI value (add SI pc 4)))
384 (decode (value pc) (add SI value (add SI pc 4)))
396 (decode (value pc) (add SI (sll value 1) (add SI pc 2)))
Dfr30.cpu41 (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by.
68 (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
126 ; This is how to fetch and decode an instruction.
141 ; RESERVED: bits are not used to decode insn, must be all 0
Dip2k.cpu114 ; RESERVED: bits are not used to decode insn, must be all 0
135 ; (decode (value pc) (sll WI value 13))
140 ; (decode (value pc) (sll WI value 13))
Dlm32.cpu42 (decode-assist (31 30 29 28 27 26))
Depiphany.cpu72 (decode-assist (3 2 1 0)) ; CGEN can figure this out
125 ; RESERVED: bits are not used to decode insn, must be all 0
229 (sequence () ;decode
/toolchain/binutils/binutils-2.25/opcodes/po/
DPOTFILES.in151 msp430-decode.c
176 rl78-decode.c
178 rx-decode.c
/toolchain/binutils/binutils-2.25/include/
Dxtensa-isa-internal.h86 xtensa_immed_decode_fn decode; /* Decode the value from the field. */ member
/toolchain/binutils/binutils-2.25/bfd/
Dxtensa-isa.c1084 || (test_val = *valp, (*intop->decode) (&test_val)) in xtensa_operand_encode()
1107 if (!intop->decode) in xtensa_operand_decode()
1110 if ((*intop->decode) (valp)) in xtensa_operand_decode()
/toolchain/binutils/binutils-2.25/include/opcode/
DChangeLog-91032005 32 bit word and we have to encode/decode both.
2309 * sparc.h (sparc_{encode,decode}_sparclet_cpreg): Declare.
2394 * sparc.h (sparc_{encode,decode}_prefetch): Declare.
2398 * sparc.h (sparc_{encode,decode}_{asi,membar}): Declare.
/toolchain/binutils/binutils-2.25/binutils/
DChangeLog-2008741 decode them.

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