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Searched refs:encode (Results 1 – 25 of 42) sorted by relevance

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/toolchain/binutils/binutils-2.25/cpu/
Dsimplify.inc44 ; Normally, fields are unsigned and have no encode/decode needs.
53 (define-pmacro (df name comment attrs start length mode encode decode)
54 "Shorthand form of normal fields requiring mode, encode/decode."
55 (define-full-ifield name comment attrs start length mode encode decode)
78 ; default encode/decode support.
Dxstormy16.cpu340 (encode (value pc) (sub HI value #x7F00))
359 (encode (value pc) (sub SI value (add SI pc 2)))
371 (encode (value pc) (sub SI value (add SI pc 4)))
383 (encode (value pc) (sub SI value (add SI pc 4)))
395 (encode (value pc) (sra SI (sub SI value (add SI pc 2)) 1))
Dip2k.cpu134 ; (encode (value pc) (srl WI value 13))
139 ; (encode (value pc) (srl WI value 13))
Dcris.cpu1414 x-start x-length x-mode x-encode x-decode)
1424 (.splice encode (.unsplice x-encode))
/toolchain/binutils/binutils-2.25/gas/doc/
Dc-i386.texi223 This option specifies that the assembler should encode SSE instructions
242 These options control how the assembler should encode scalar AVX
243 instructions. @option{-mavxscalar=@var{128}} will encode scalar
245 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
253 These options control how the assembler should encode length-ignored
254 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
257 encode LIG EVEX instructions with 256bit and 512bit vector length,
264 These options control how the assembler should encode w-ignored (WIG)
265 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
267 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
[all …]
Dc-xtensa.texi154 The assembler will automatically search for a format that can encode the
Dc-arm.texi491 targets it will encode either the @samp{R_ARM_CALL} or
/toolchain/binutils/binutils-2.25/include/
Dxtensa-isa-internal.h85 xtensa_immed_encode_fn encode; /* Encode the operand value. */ member
/toolchain/binutils/binutils-2.25/bfd/
Dxtensa-isa.c1034 if (!intop->encode) in xtensa_operand_encode()
1083 if ((*intop->encode) (valp) in xtensa_operand_encode()
DChangeLog-2008458 encode and decode them.
495 to encode them.
DChangeLog-20093122 * elf32-spu.c (spu_elf_relocate_section): Only encode overlay index
5088 (spu_elf_relocate_section): For soft-icache encode overlay index
/toolchain/binutils/binutils-2.25/opcodes/
Dmsp430-decode.opc400 /* The helper functions encode for source, but it's
DChangeLog-92972065 (sparc_{encode,decode}_sparclet_cpreg): New functions.
2488 (sparc_{encode,decode}_prefetch): New functions.
2505 (sparc_{encode,decode}_{asi,membar}): New functions.
/toolchain/binutils/binutils-2.25/include/opcode/
DChangeLog478 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
480 encode the opcodes in the same way as TI assembler does.
1965 (previously one had to explicitly encode a rex64 prefix). Re-enable
DChangeLog-91032005 32 bit word and we have to encode/decode both.
2309 * sparc.h (sparc_{encode,decode}_sparclet_cpreg): Declare.
2394 * sparc.h (sparc_{encode,decode}_prefetch): Declare.
2398 * sparc.h (sparc_{encode,decode}_{asi,membar}): Declare.
/toolchain/binutils/binutils-2.25/gas/
DChangeLog-20071561 (do_t_add_sub): Correctly encode subs pc, lr, #const.
1562 (do_t_mov_cmp): Correctly encode movs pc, lr.
1939 register operands, encode destination in i.rm.regmem if its
2388 encode expression symbols as mangled complex relocation symbols (when
DNEWS113 * New command line option -msse2avx for x86 target to encode SSE
DChangeLog-20061178 and encode the current instruction as if it were that opcode.
1916 (do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D
DChangeLog807 encode.
DChangeLog-20131669 encode register pair numbers when required.
DChangeLog-20101497 * config/tc-arm.c (do_t_mov_cmp): In unified syntax encode movs as
/toolchain/binutils/binutils-2.25/ld/emultempl/
Dxtensaelf.em427 detailed instruction encode/decode operations (such as are
/toolchain/binutils/binutils-2.25/gas/po/
Dgas.pot6901 msgid "can't encode register '%s%s' in an instruction requiring REX prefix."
7477 msgid " -msse2avx encode SSE instructions with VEX prefix\n"
7497 " -mavxscalar=[128|256] encode scalar AVX instructions with specific "
7505 " -mevexlig=[128|256|512] encode scalar EVEX instructions with specific "
7513 " -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W "
7522 " encode EVEX instructions with specific EVEX.RC "
10262 #. We already tried to encode as an extended GET/SET.
17265 "-+\t\t\thash encode names longer than 31 characters\n"
17615 msgid "cannot encode opcode \"%s\""
17978 msgid "cannot encode opcode \"%s\" in the given format \"%s\""
Duk.po6833 msgid "can't encode register '%s%s' in an instruction requiring REX prefix."
7403 msgid " -msse2avx encode SSE instructions with VEX prefix\n"
7427 " -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n"
7436 " -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n"
7445 " -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n"
10179 #. We already tried to encode as an extended GET/SET.
17129 "-+\t\t\thash encode names longer than 31 characters\n"
17475 msgid "cannot encode opcode \"%s\""
17829 msgid "cannot encode opcode \"%s\" in the given format \"%s\""
Dja.po5836 msgid "can't encode register '%s%s' in an instruction requiring REX prefix."
6291 msgid " -msse2avx encode SSE instructions with VEX prefix\n"
6306 " -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n"
14619 "-+\t\t\thash encode names longer than 31 characters\n"
14883 msgid "cannot encode opcode \"%s\""
15241 msgid "cannot encode opcode \"%s\" in the given format \"%s\""

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