| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| D | armv7-a+virt.s | 8 mrs r1, R8_usr
9 mrs r1, R9_usr
10 mrs r1, R10_usr
11 mrs r1, R11_usr
12 mrs r1, R12_usr
13 mrs r1, SP_usr
14 mrs r1, LR_usr
15 mrs r1, R8_fiq
16 mrs r1, R9_fiq
17 mrs r1, R10_fiq
[all …]
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| D | armv7-a+virt.d | 11 0[0-9a-f]+ <[^>]+> e1001200 mrs r1, R8_usr
12 0[0-9a-f]+ <[^>]+> e1011200 mrs r1, R9_usr
13 0[0-9a-f]+ <[^>]+> e1021200 mrs r1, R10_usr
14 0[0-9a-f]+ <[^>]+> e1031200 mrs r1, R11_usr
15 0[0-9a-f]+ <[^>]+> e1041200 mrs r1, R12_usr
16 0[0-9a-f]+ <[^>]+> e1051200 mrs r1, SP_usr
17 0[0-9a-f]+ <[^>]+> e1061200 mrs r1, LR_usr
18 0[0-9a-f]+ <[^>]+> e1081200 mrs r1, R8_fiq
19 0[0-9a-f]+ <[^>]+> e1091200 mrs r1, R9_fiq
20 0[0-9a-f]+ <[^>]+> e10a1200 mrs r1, R10_fiq
[all …]
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| D | armv8-a.s | 12 stlb r1, [r1]
15 stlh r1, [r1]
18 stl r1, [r1]
20 stlexb r0, r1, [r14]
21 stlexb r1, r14, [r0]
22 stlexb r14, r0, [r1]
23 stlexh r0, r1, [r14]
24 stlexh r1, r14, [r0]
25 stlexh r14, r0, [r1]
26 stlex r0, r1, [r14]
[all …]
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| D | inst.s | 6 mov r1, r2
19 movcc r1, r2
20 movcs r1, r3
23 movvs r1, r8
24 movvc SB, r1, lsr #31
28 movul r1, r3
32 add r0, r1, #10
35 add r1, r2, r3, lsl r1
37 and r0, r1, #10
40 and r1, r2, r3, lsl r1
[all …]
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| D | thumb2_relax.d | 7 0+000 <[^>]+> 7829 ldrb r1, \[r5, #0\]
8 0+002 <[^>]+> f895 1023 ldrb.w r1, \[r5, #35\].*
9 0+006 <[^>]+> 7fe9 ldrb r1, \[r5, #31\]
10 0+008 <[^>]+> f895 101f ldrb.w r1, \[r5, #31\]
11 0+00c <[^>]+> f815 1c1f ldrb.w r1, \[r5, #-31\]
12 0+010 <[^>]+> f815 1b1f ldrb.w r1, \[r5\], #31
13 0+014 <[^>]+> f815 1b1f ldrb.w r1, \[r5\], #31
14 0+018 <[^>]+> f815 1f1f ldrb.w r1, \[r5, #31\]!
15 0+01c <[^>]+> f815 1d1f ldrb.w r1, \[r5, #-31\]!
16 0+020 <[^>]+> 5d29 ldrb r1, \[r5, r4\]
[all …]
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| D | sp-pc-validations-bad.s | 11 ldr r0,[r1,pc, LSL #2] @ Unpredictable
12 ldr r0,[r1,pc, LSL #2]! @ ditto
13 ldr r0,[r1],pc, LSL #2 @ ditto
14 ldr r0,[pc,r1, LSL #2]! @ ditto
15 ldr r0,[pc],r1, LSL #2 @ ditto
27 ldrb pc,[r0,r1, LSL #2] @ Unpredictable
28 ldrb pc,[r0,r1, LSL #2]! @ ditto
29 ldrb pc,[r0],r1, LSL #2 @ ditto
30 ldrb r0,[r1,pc, LSL #2] @ ditto
31 ldrb r0,[r1,pc, LSL #2]! @ ditto
[all …]
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| D | inst.d | 13 0+004 <[^>]*> e1a01002 ? mov r1, r2
19 0+01c <[^>]*> e1a01002 ? mov r1, r2
26 0+038 <[^>]*> 31a01002 ? movcc r1, r2
27 0+03c <[^>]*> 21a01003 ? movcs r1, r3
30 0+048 <[^>]*> 61a01008 ? movvs r1, r8
31 0+04c <[^>]*> 71a09fa1 ? lsrvc r9, r1, #31
35 0+05c <[^>]*> 31a01003 ? movcc r1, r3
38 0+068 <[^>]*> e281000a ? add r0, r1, #10
41 0+074 <[^>]*> e0821113 ? add r1, r2, r3, lsl r1
42 0+078 <[^>]*> e201000a ? and r0, r1, #10
[all …]
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| D | arm7t.s | 5 ldrh r0, [r1]
6 ldrh r0, [r1]!
7 ldrh r0, [r1, r2]
8 ldrh r0, [r1, r2]!
9 ldrh r0, [r1,#0x0C]
10 ldrh r0, [r1,#0x0C]!
11 ldrh r0, [r1,#-0x0C]
12 ldrh r0, [r1], r2
18 strh r0, [r1]
19 strh r0, [r1]!
[all …]
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| D | wince_inst.d | 15 0+004 <[^>]*> e1a01002 ? mov r1, r2
21 0+01c <[^>]*> e1a01002 ? mov r1, r2
28 0+038 <[^>]*> 31a01002 ? movcc r1, r2
29 0+03c <[^>]*> 21a01003 ? movcs r1, r3
32 0+048 <[^>]*> 61a01008 ? movvs r1, r8
33 0+04c <[^>]*> 71a09fa1 ? lsrvc r9, r1, #31
37 0+05c <[^>]*> 31a01003 ? movcc r1, r3
40 0+068 <[^>]*> e281000a ? add r0, r1, #10
43 0+074 <[^>]*> e0821113 ? add r1, r2, r3, lsl r1
44 0+078 <[^>]*> e201000a ? and r0, r1, #10
[all …]
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| D | ldst-offset0.s | 5 ldr r1, [r2, #-0]
6 ldr r1, [r2, #-1+1]
8 ldr r1, [r2, #1-1]
9 ldr r1, [r2, #0]
11 ldr r1, [r2, #-0]!
12 ldr r1, [r2, #-1+1]!
14 ldr r1, [r2, #1-1]!
15 ldr r1, [r2, #0]!
17 ldr r1, [r2], #-0
18 ldr r1, [r2], #-1+1
[all …]
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| D | sp-pc-validations-bad-t.s | 43 LOAD [r0, r1]
44 LOADw [r0, r1]
45 LOADw [r0, r1, LSL #2]
66 ldrb pc,[r0,r1] @ low reg
67 ldrb r0,[pc,r1] @ ditto
68 ldrb r0,[r1,pc] @ ditto
69 ldrb.w pc,[r0,r1,LSL #1] @ => PLD
70 ldrb.w sp,[r0,r1] @ Unpredictable
79 ldrd pc, r0, [r1] @ BadReg
80 ldrd sp, r0, [r1] @ ditto
[all …]
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| D | arch7em.s | 14 pkhtb r1, r2, r3
15 pkhtb r1, r2, r3, asr #0x11
18 qadd r1, r2, r3
19 qadd16 r1, r2, r3
20 qadd8 r1, r2, r3
21 qasx r1, r2, r3
22 qaddsubx r1, r2, r3
23 qdadd r1, r2, r3
24 qdsub r1, r2, r3
25 qsub r1, r2, r3
[all …]
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| D | armv8-a.d | 12 0[0-9a-f]+ <[^>]+> e1c1fc91 stlb r1, \[r1\]
15 0[0-9a-f]+ <[^>]+> e1e1fc91 stlh r1, \[r1\]
18 0[0-9a-f]+ <[^>]+> e181fc91 stl r1, \[r1\]
20 0[0-9a-f]+ <[^>]+> e1ce0e91 stlexb r0, r1, \[lr\]
21 0[0-9a-f]+ <[^>]+> e1c01e9e stlexb r1, lr, \[r0\]
22 0[0-9a-f]+ <[^>]+> e1c1ee90 stlexb lr, r0, \[r1\]
23 0[0-9a-f]+ <[^>]+> e1ee0e91 stlexh r0, r1, \[lr\]
24 0[0-9a-f]+ <[^>]+> e1e01e9e stlexh r1, lr, \[r0\]
25 0[0-9a-f]+ <[^>]+> e1e1ee90 stlexh lr, r0, \[r1\]
26 0[0-9a-f]+ <[^>]+> e18e0e91 stlex r0, r1, \[lr\]
[all …]
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/ |
| D | invalid-ar.s | 2 mov.i r1 = ar0
3 mov.i r1 = ar1
4 mov.i r1 = ar2
5 mov.i r1 = ar3
6 mov.i r1 = ar4
7 mov.i r1 = ar5
8 mov.i r1 = ar6
9 mov.i r1 = ar7
10 mov.i r1 = ar8
11 mov.i r1 = ar9
[all …]
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mn10300/ |
| D | am33_7.s | 3 cmp_add 4,r1,r2,r3
4 cmp_add 4,r1,2,r3
5 cmp_sub 4,r1,r2,r3
6 cmp_sub 4,r1,2,r3
7 cmp_mov 4,r1,r2,r3
8 cmp_mov 4,r1,2,r3
9 cmp_asr 4,r1,r2,r3
10 cmp_asr 4,r1,2,r3
11 cmp_lsr 4,r1,r2,r3
12 cmp_lsr 4,r1,2,r3
[all …]
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| D | am33_6.s | 3 add_add r4,r1,r2,r3
4 add_add r4,r1,2,r3
5 add_sub r4,r1,r2,r3
6 add_sub r4,r1,2,r3
7 add_cmp r4,r1,r2,r3
8 add_cmp r4,r1,2,r3
9 add_mov r4,r1,r2,r3
10 add_mov r4,r1,2,r3
11 add_asr r4,r1,r2,r3
12 add_asr r4,r1,2,r3
[all …]
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| D | am33_8.s | 3 xor_add r4,r1,r2,r3
4 xor_add r4,r1,2,r3
5 xor_sub r4,r1,r2,r3
6 xor_sub r4,r1,2,r3
7 xor_cmp r4,r1,r2,r3
8 xor_cmp r4,r1,2,r3
9 xor_mov r4,r1,r2,r3
10 xor_mov r4,r1,2,r3
11 xor_asr r4,r1,r2,r3
12 xor_asr r4,r1,2,r3
[all …]
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| D | am33_3.s | 3 mov 16,r1
4 movu 16,r1
5 add 16,r1
6 addc 16,r1
7 sub 16,r1
8 subc 16,r1
9 cmp 16,r1
11 and 16,r1
12 or 16,r1
13 xor 16,r1
[all …]
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/ |
| D | video2.s | 60 r0 = byteop3p (r1:0, r3:2) (lo) ;
61 r1 = byteop3p (r1:0, r3:2) (hi) ; define
62 r2 = byteop3p (r1:0, r3:2) (lo, r) ;
63 r3 = byteop3p (r1:0, r3:2) (hi, r) ;
64 r4 = byteop3p (r3:2, r1:0) (lo) ;
65 r5 = byteop3p (r3:2, r1:0) (hi) ;
66 r6 = byteop3p (r3:2, r1:0) (lo, r) ;
67 r7 = byteop3p (r3:2, r1:0) (hi, r) ;
78 (r7,r0) = BYTEOP16P ( r3:2,r1:0 ) ;
79 (r1,r2) = byteop16p (r3:2,r1:0) ;
[all …]
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/d30v/ |
| D | inst.s | 6 add r1,r2,r3
10 add2h r1,r2,r3
14 addc r1,r2,r3
18 addhlll r1,r2,r3
22 addhllh r1,r2,r3
26 addhlhl r1,r2,r3
30 addhlhh r1,r2,r3
34 addhhll r1,r2,r3
38 addhhlh r1,r2,r3
42 addhhhl r1,r2,r3
[all …]
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| /toolchain/binutils/binutils-2.25/cpu/ |
| D | lm32.cpu | 80 (r0 0) (r1 1) (r2 2) (r3 3)
119 (dnf f-r1 "register index 1 field" () 20 5)
142 (dnop r1 "register 1" () h-gr f-r1)
280 "add $r2,$r0,$r1"
281 (+ OP_ADD r0 r1 r2 (f-resv0 0))
282 (set r2 (add r0 r1))
287 "addi $r1,$r0,$imm"
288 (+ OP_ADDI r0 r1 imm)
289 (set r1 (add r0 (ext SI (trunc HI imm))))
294 "and $r2,$r0,$r1"
[all …]
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/nds32/ |
| D | alu-1.s | 2 add $r0, $r1, $r2
3 and $r0, $r1, $r2
4 cmovn $r0, $r1, $r2
5 cmovz $r0, $r1, $r2
7 nor $r0, $r1, $r2
8 or $r0, $r1, $r2
9 rotr $r0, $r1, $r2
10 rotri $r0, $r1, 1
11 seb $r0, $r1
12 seh $r0, $r1
[all …]
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| D | alu-1.d | 10 0+0000 <[^>]*> add \$r0, \$r1, \$r2
11 0+0004 <[^>]*> and \$r0, \$r1, \$r2
12 0+0008 <[^>]*> cmovn \$r0, \$r1, \$r2
13 0+000c <[^>]*> cmovz \$r0, \$r1, \$r2
15 0+0014 <[^>]*> nor \$r0, \$r1, \$r2
16 0+0018 <[^>]*> or \$r0, \$r1, \$r2
17 0+001c <[^>]*> rotr \$r0, \$r1, \$r2
18 0+0020 <[^>]*> rotri \$r0, \$r1, #1
19 0+0024 <[^>]*> seb \$r0, \$r1
20 0+0028 <[^>]*> seh \$r0, \$r1
[all …]
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cr16/ |
| D | loadd_test.s | 7 loadd 0x0,(r1,r0)
8 loadd 0xff,(r1,r0)
12 loadd 0x7A1234,(r1,r0)
13 loadd 0xBA1234,(r1,r0)
14 loadd 0xffffff,(r2,r1)
18 loadd [r12]0x0,(r1,r0)
19 loadd [r13]0x0,(r1,r0)
20 loadd [r12]0xff,(r1,r0)
21 loadd [r13]0xff,(r1,r0)
28 loadd [r12]0x4567,(r2,r1)
[all …]
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| D | stord_test.s | 7 stord (r1,r0),0x0
8 stord (r1,r0),0xff
12 stord (r1,r0),0x7A1234
13 stord (r1,r0),0xBA1234
14 stord (r2,r1),0xffffff
18 stord (r1,r0),[r12]0x0
19 stord (r1,r0),[r13]0x0
20 stord (r1,r0),[r12]0xff
21 stord (r1,r0),[r13]0xff
28 stord (r2,r1),[r12]0x4567
[all …]
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