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/toolchain/binutils/binutils-2.25/cpu/
Dsh64-compact.cpu199 (dshcf f-rn "Register selector n" () 11 4)
259 (dshcop rn "Right general purpose register" () h-grc f-rn)
262 (dshcop frn "Single precision register" () h-frc f-rn)
284 (dshcop rn64 "Register n (64 bits)" () h-gr f-rn)
309 (attrs (ISA compact)) (type h-frc) (index f-rn))
329 "add $rm, $rn"
330 (+ (f-op4 3) rn rm (f-sub4 12))
331 (set rn (add rn rm)))
335 "add #$imm8, $rn"
336 (+ (f-op4 7) rn imm8)
[all …]
Dsh64-media.cpu138 (dshmop rn "Right general purpose reg" () h-gr f-right)
189 "add $rm, $rn, $rd"
190 (+ (f-op 0) rm (f-ext 9) rn rd (f-rsvd 0))
191 (set rd (add rm rn)))
195 "add.l $rm, $rn, $rd"
196 (+ (f-op 0) rm (f-ext 8) rn rd (f-rsvd 0))
197 (set rd (add (subword SI rm 1) (subword SI rn 1))))
213 "addz.l $rm, $rn, $rd"
214 (+ (f-op 0) rm (f-ext 12) rn rd (f-rsvd 0))
215 (set rd (zext DI (add (subword SI rm 1) (subword SI rn 1)))))
[all …]
Dmep-core.cpu346 (dnf f-rn "register n" (all-mep-core-isas) 4 4)
680 (dnop rn "register Rn" (all-mep-core-isas) h-gpr f-rn)
690 … rnc "register Rn holding char" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn)
691 … rnuc "register Rn holding unsigned char" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn)
692 … rns "register Rn holding short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn)
693 … rnus "register Rn holding unsigned short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn)
694 … rnl "register Rn holding long" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn)
695 … rnul "register Rn holding unsigned long" (all-mep-core-isas (CDATA ULONG)) h-gpr f-rn)
772 (dnop cimm4 "cache immed'te (4 bits)" (all-mep-core-isas) h-uint f-rn)
1353 "extb $rn"
[all …]
Dmep-c5.cpu36 "stcb $rn,($rma)"
37 (+ MAJ_7 rn rma (f-sub4 12))
38 (c-call VOID "do_stcb" rn (and rma #xffff))
39 ((mep (unit u-use-gpr (in usereg rn))
45 "ldcb $rn,($rma)"
46 (+ MAJ_7 rn rma (f-sub4 13))
47 (set rn (c-call SI "do_ldcb" (and rma #xffff)))
51 (unit u-ldcb-gpr (out loadreg rn)))))
72 "casb3 $rl5,$rn,($rm)"
73 (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x0))
[all …]
Dmep-h1.cpu25 "stcb $rn,($rma)"
26 (+ MAJ_7 rn rma (f-sub4 12))
27 (c-call VOID "do_stcb" rn (and rma #xffff))
28 ((mep (unit u-use-gpr (in usereg rn))
34 "ldcb $rn,($rma)"
35 (+ MAJ_7 rn rma (f-sub4 13))
36 (set rn (c-call SI "do_ldcb" (and rma #xffff)))
40 (unit u-ldcb-gpr (out loadreg rn)))))
Depiphany.cpu170 (dnf f-rn "short rn" () 12 3) ;; RN
174 (dnf f-rn-x "extension rn" () 28 3) ;; RN
269 (x-reg-field rn) ; f-rn6
961 (short-regs rn n h-registers "source register")
1221 ("jr $rn")
1222 (+ OP4_FLOW16 (f-opc-8-5 #x14) (f-dc-15-3 #x0) (f-dc-9-1 #x0) rn)
1223 (set pc rn)
1239 (+ OP4_MISC (f-opc-8-5 #x14) (f-opc-19-4 #x2) (f-rn 6) (f-rn-x 1)
1266 ("jalr $rn")
1267 (+ OP4_FLOW16 (f-opc-8-5 #x15) (f-dc-15-3 #x0) (f-dc-9-1 #x0) rn)
[all …]
Dmep-sample-ucidsp.cpu105 "uci $rn,$rm,$code16"
106 (+ MAJ_15 rn rm (f-sub4 2) code16)
115 "dsp $rn,$rm,$code16"
116 (+ MAJ_15 rn rm (f-sub4 0) code16)
/toolchain/binutils/binutils-2.25/opcodes/
Dsh-dis.c36 int rn, in print_movxy() argument
53 fprintf_fn (stream, "@r%d", rn); in print_movxy()
60 fprintf_fn (stream, "@r%d+", rn); in print_movxy()
64 fprintf_fn (stream, "@r%d+r8", rn); in print_movxy()
68 fprintf_fn (stream, "@r%d+r9", rn); in print_movxy()
501 int rn = 0; in print_insn_sh() local
639 rn = nibs[n]; in print_insn_sh()
647 rn = (nibs[n] & 0xc) >> 2; in print_insn_sh()
650 rn = (nibs[n] & 0xc) >> 2; in print_insn_sh()
658 rn = nibs[n]; in print_insn_sh()
[all …]
Dh8300-dis.c179 int rn, in print_one_arg() argument
205 outfn (stream, "%s", regnames[rn]); in print_one_arg()
209 outfn (stream, "%s", wregnames[rn]); in print_one_arg()
213 outfn (stream, "%s", lregnames[rn]); in print_one_arg()
223 outfn (stream, "%s.b", regnames[rn < 8 ? rn + 8 : rn]); in print_one_arg()
228 outfn (stream, "%s.w", wregnames[rn < 8 ? rn : rn - 8]); in print_one_arg()
232 outfn (stream, "%s.l", lregnames[rn]); in print_one_arg()
237 outfn (stream, "@%s+", pregnames[rn]); in print_one_arg()
240 outfn (stream, "@%s-", pregnames[rn]); in print_one_arg()
243 outfn (stream, "@+%s", pregnames[rn]); in print_one_arg()
[all …]
Dh8500-dis.c95 int rn = 0; in print_insn_h8500() local
127 rn = buffer[byte] & 0x7; in print_insn_h8500()
221 func (stream, "@(0x%x:16,r%d)", disp, rn); in print_insn_h8500()
224 func (stream, "@(0x%x:8 (%d),r%d)", disp & 0xff, disp, rn); in print_insn_h8500()
240 func (stream, "r%d", rn); in print_insn_h8500()
249 func (stream, "@-r%d", rn); in print_insn_h8500()
252 func (stream, "@r%d+", rn); in print_insn_h8500()
255 func (stream, "@r%d", rn); in print_insn_h8500()
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
Dldr-t.s14 @!(rt == r15) && rn == r15
18 @rt == r15 && !(rn == r15)
22 @rt == r15 && rn == r15
71 @!(rt == 15 || rn == 15)
Dldr.s13 @ !(rt == r15) && (rn == r15)
17 @ (rt == r15) && !(rn == r15)
21 @ ((rt == r15) && ((rn == r15)
Dldr-t-bad.s10 @rt == r15 && rn == r15
46 @rt == 15 || rn == 15
Dthumb2_ldmstm.s48 @ as written, but gas translates (stm|ldm) rn(!), {rd} into an
49 @ equivalent, and well-defined, (ldr, str) rd, [rn], (#4).
/toolchain/binutils/binutils-2.25/gas/doc/
Dc-i860.texi132 The pseudo-instruction @code{mov imm,%rn} (where the immediate does
135 orh large_imm@@h,%r0,%rn
136 or large_imm@@l,%rn,%rn
140 For example, the pseudo-instruction @code{ld.b addr_exp(%rx),%rn}
144 ld.l addr_exp@@l(%r31),%rn
152 For instance, the pseudo-instruction @code{adds large_imm,%rx,%rn} expands to:
156 adds %r31,%rx,%rn
161 The pseudo-instruction @code{or large_imm,%rx,%rn} results in:
164 or large_imm@@l,%r31,%rn
170 andnot (-1 - large_imm)@@l,%r31,%rn
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/
Daddsub.s27 .macro adjust_rm op, rd, rn, rm_r, rm_n, extend, amount
35 \op \rd, \rn, W\()\rm_n, \extend
37 \op \rd, \rn, W\()\rm_n, \extend #\amount
46 \op \rd, \rn, \rm_r\()\rm_n, \extend
48 \op \rd, \rn, \rm_r\()\rm_n, \extend #\amount
Dneon-frint.s4 .macro frint_main rd rn argument
7 frint\rounding_mode \rd\().\reg_shape, \rn\().\reg_shape
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
Dx86-64-evex-lig.s9 vaddsd {rn-sae}, %xmm28, %xmm29, %xmm30{%k7} # AVX512
22 vaddss {rn-sae}, %xmm28, %xmm29, %xmm30{%k7} # AVX512
901 vcvtsd2si {rn-sae}, %xmm30, %eax # AVX512
905 vcvtsd2si {rn-sae}, %xmm30, %ebp # AVX512
909 vcvtsd2si {rn-sae}, %xmm30, %r13d # AVX512
914 vcvtsd2si {rn-sae}, %xmm30, %rax # AVX512
918 vcvtsd2si {rn-sae}, %xmm30, %r8 # AVX512
925 vcvtsd2ss {rn-sae}, %xmm28, %xmm29, %xmm30{%k7} # AVX512
947 vcvtsi2sdq %rax, {rn-sae}, %xmm29, %xmm30 # AVX512
952 vcvtsi2sdq %r8, {rn-sae}, %xmm29, %xmm30 # AVX512
[all …]
Devex-lig.s9 vaddsd {rn-sae}, %xmm4, %xmm5, %xmm6{%k7} # AVX512
22 vaddss {rn-sae}, %xmm4, %xmm5, %xmm6{%k7} # AVX512
887 vcvtsd2si {rn-sae}, %xmm6, %eax # AVX512
891 vcvtsd2si {rn-sae}, %xmm6, %ebp # AVX512
898 vcvtsd2ss {rn-sae}, %xmm4, %xmm5, %xmm6{%k7} # AVX512
910 vcvtsi2ssl %eax, {rn-sae}, %xmm5, %xmm6 # AVX512
914 vcvtsi2ssl %ebp, {rn-sae}, %xmm5, %xmm6 # AVX512
929 vcvtss2si {rn-sae}, %xmm6, %eax # AVX512
933 vcvtss2si {rn-sae}, %xmm6, %ebp # AVX512
946 vdivsd {rn-sae}, %xmm4, %xmm5, %xmm6{%k7} # AVX512
[all …]
Dx86-64-evex-lig256.d14 [ ]*[a-f0-9]+: 62 01 97 17 58 f4 vaddsd \{rn-sae\},%xmm28,%xmm29,%xmm30\{%k7\}
26 [ ]*[a-f0-9]+: 62 01 16 17 58 f4 vaddss \{rn-sae\},%xmm28,%xmm29,%xmm30\{%k7\}
808 [ ]*[a-f0-9]+: 62 91 7f 18 2d c6 vcvtsd2si \{rn-sae\},%xmm30,%eax
812 [ ]*[a-f0-9]+: 62 91 7f 18 2d ee vcvtsd2si \{rn-sae\},%xmm30,%ebp
816 [ ]*[a-f0-9]+: 62 11 7f 18 2d ee vcvtsd2si \{rn-sae\},%xmm30,%r13d
820 [ ]*[a-f0-9]+: 62 91 ff 18 2d c6 vcvtsd2si \{rn-sae\},%xmm30,%rax
824 [ ]*[a-f0-9]+: 62 11 ff 18 2d c6 vcvtsd2si \{rn-sae\},%xmm30,%r8
830 [ ]*[a-f0-9]+: 62 01 97 17 5a f4 vcvtsd2ss \{rn-sae\},%xmm28,%xmm29,%xmm30\{%k7\}
850 [ ]*[a-f0-9]+: 62 61 97 10 2a f0 vcvtsi2sd %rax,\{rn-sae\},%xmm29,%xmm30
855 [ ]*[a-f0-9]+: 62 41 97 10 2a f0 vcvtsi2sd %r8,\{rn-sae\},%xmm29,%xmm30
[all …]
Dx86-64-evex-lig512.d14 [ ]*[a-f0-9]+: 62 01 97 17 58 f4 vaddsd \{rn-sae\},%xmm28,%xmm29,%xmm30\{%k7\}
26 [ ]*[a-f0-9]+: 62 01 16 17 58 f4 vaddss \{rn-sae\},%xmm28,%xmm29,%xmm30\{%k7\}
808 [ ]*[a-f0-9]+: 62 91 7f 18 2d c6 vcvtsd2si \{rn-sae\},%xmm30,%eax
812 [ ]*[a-f0-9]+: 62 91 7f 18 2d ee vcvtsd2si \{rn-sae\},%xmm30,%ebp
816 [ ]*[a-f0-9]+: 62 11 7f 18 2d ee vcvtsd2si \{rn-sae\},%xmm30,%r13d
820 [ ]*[a-f0-9]+: 62 91 ff 18 2d c6 vcvtsd2si \{rn-sae\},%xmm30,%rax
824 [ ]*[a-f0-9]+: 62 11 ff 18 2d c6 vcvtsd2si \{rn-sae\},%xmm30,%r8
830 [ ]*[a-f0-9]+: 62 01 97 17 5a f4 vcvtsd2ss \{rn-sae\},%xmm28,%xmm29,%xmm30\{%k7\}
850 [ ]*[a-f0-9]+: 62 61 97 10 2a f0 vcvtsi2sd %rax,\{rn-sae\},%xmm29,%xmm30
855 [ ]*[a-f0-9]+: 62 41 97 10 2a f0 vcvtsi2sd %r8,\{rn-sae\},%xmm29,%xmm30
[all …]
Dx86-64-evex-lig512-intel.d14 [ ]*[a-f0-9]+: 62 01 97 17 58 f4 vaddsd xmm30\{k7\},xmm29,xmm28,\{rn-sae\}
26 [ ]*[a-f0-9]+: 62 01 16 17 58 f4 vaddss xmm30\{k7\},xmm29,xmm28,\{rn-sae\}
808 [ ]*[a-f0-9]+: 62 91 7f 18 2d c6 vcvtsd2si eax,xmm30,\{rn-sae\}
812 [ ]*[a-f0-9]+: 62 91 7f 18 2d ee vcvtsd2si ebp,xmm30,\{rn-sae\}
816 [ ]*[a-f0-9]+: 62 11 7f 18 2d ee vcvtsd2si r13d,xmm30,\{rn-sae\}
820 [ ]*[a-f0-9]+: 62 91 ff 18 2d c6 vcvtsd2si rax,xmm30,\{rn-sae\}
824 [ ]*[a-f0-9]+: 62 11 ff 18 2d c6 vcvtsd2si r8,xmm30,\{rn-sae\}
830 [ ]*[a-f0-9]+: 62 01 97 17 5a f4 vcvtsd2ss xmm30\{k7\},xmm29,xmm28,\{rn-sae\}
850 [ ]*[a-f0-9]+: 62 61 97 10 2a f0 vcvtsi2sd xmm30,xmm29,\{rn-sae\},rax
855 [ ]*[a-f0-9]+: 62 41 97 10 2a f0 vcvtsi2sd xmm30,xmm29,\{rn-sae\},r8
[all …]
Dx86-64-evex-lig256-intel.d14 [ ]*[a-f0-9]+: 62 01 97 17 58 f4 vaddsd xmm30\{k7\},xmm29,xmm28,\{rn-sae\}
26 [ ]*[a-f0-9]+: 62 01 16 17 58 f4 vaddss xmm30\{k7\},xmm29,xmm28,\{rn-sae\}
808 [ ]*[a-f0-9]+: 62 91 7f 18 2d c6 vcvtsd2si eax,xmm30,\{rn-sae\}
812 [ ]*[a-f0-9]+: 62 91 7f 18 2d ee vcvtsd2si ebp,xmm30,\{rn-sae\}
816 [ ]*[a-f0-9]+: 62 11 7f 18 2d ee vcvtsd2si r13d,xmm30,\{rn-sae\}
820 [ ]*[a-f0-9]+: 62 91 ff 18 2d c6 vcvtsd2si rax,xmm30,\{rn-sae\}
824 [ ]*[a-f0-9]+: 62 11 ff 18 2d c6 vcvtsd2si r8,xmm30,\{rn-sae\}
830 [ ]*[a-f0-9]+: 62 01 97 17 5a f4 vcvtsd2ss xmm30\{k7\},xmm29,xmm28,\{rn-sae\}
850 [ ]*[a-f0-9]+: 62 61 97 10 2a f0 vcvtsi2sd xmm30,xmm29,\{rn-sae\},rax
855 [ ]*[a-f0-9]+: 62 41 97 10 2a f0 vcvtsi2sd xmm30,xmm29,\{rn-sae\},r8
[all …]
Dx86-64-avx512f.s10 vaddpd {rn-sae}, %zmm28, %zmm29, %zmm30 # AVX512F
29 vaddps {rn-sae}, %zmm28, %zmm29, %zmm30 # AVX512F
47 vaddsd {rn-sae}, %xmm28, %xmm29, %xmm30{%k7} # AVX512F
60 vaddss {rn-sae}, %xmm28, %xmm29, %xmm30{%k7} # AVX512F
2500 vcvtdq2ps {rn-sae}, %zmm29, %zmm30 # AVX512F
2518 vcvtpd2dq {rn-sae}, %zmm29, %ymm30{%k7} # AVX512F
2536 vcvtpd2ps {rn-sae}, %zmm29, %ymm30{%k7} # AVX512F
2554 vcvtpd2udq {rn-sae}, %zmm29, %ymm30{%k7} # AVX512F
2583 vcvtps2dq {rn-sae}, %zmm29, %zmm30 # AVX512F
2623 vcvtps2udq {rn-sae}, %zmm29, %zmm30 # AVX512F
[all …]
/toolchain/binutils/binutils-2.25/gas/config/
Dtc-spu.c531 struct reg_name *rn; in get_reg() local
536 rn = ch_reg_name; in get_reg()
541 rn = sp_reg_name; in get_reg()
546 rn = reg_name; in get_reg()
551 if (rn[i].length > l in get_reg()
552 && 0 == strncasecmp (param, rn[i].name, rn[i].length)) in get_reg()
554 l = rn[i].length; in get_reg()
555 regno = rn[i].regno; in get_reg()

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