| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 45 std::unique_ptr<RCInfo[]> RegClass; variable
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| D | RegisterScavenging.h | 144 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1594 SDValue RegClass = in createGPRPairNode() local
1605 SDValue RegClass = in createSRegPairNode() local
1616 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1627 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode() local
1639 SDValue RegClass = in createQuadSRegsNode() local
1654 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode() local
1669 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode() local
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| D | ARMLoadStoreOptimizer.cpp | 535 unsigned ARMLoadStoreOpt::findFreeReg(const TargetRegisterClass &RegClass) { in findFreeReg()
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| /external/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 91 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ in createVirtualRegister()
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| D | TargetInstrInfo.cpp | 50 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() local
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| D | LiveIntervalAnalysis.cpp | 1454 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in splitSeparateComponents() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 191 int RegClass = Desc.OpInfo[OpIdx].RegClass; in getOperandRegClass() local
359 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in Select() local
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| D | SIInstrInfo.cpp | 1475 int RegClass = Desc.OpInfo[i].RegClass; in verifyInstruction() local
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| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 545 const TargetRegisterClass *RegClass = &X86::GR64RegClass; in emitStackProbeInline() local
2440 auto &RegClass = in adjustStackWithPops() local
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1263 for (auto &RegClass : RegClasses) { in computeSubRegLaneMasks() local
1323 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets() local
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| D | CodeGenDAGPatterns.cpp | 1491 Record *RegClass = R->getValueAsDef("RegClass"); in getImplicitType() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 1228 SDValue RegClass = CurDAG->getTargetConstant(Hexagon::DoubleRegsRegClassID, in SelectBitOp() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1769 const TargetRegisterClass *RegClass = in constrainOperandRegClass() local
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| D | ScheduleDAGRRList.cpp | 279 unsigned &RegClass, unsigned &Cost, in GetCostForDef()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3879 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) { in matchRegisterByNumber()
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