| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 50 const unsigned *Regs, unsigned Size) { in decodeRegisterClass()
228 const unsigned *Regs) { in decodeBDAddr12Operand()
238 const unsigned *Regs) { in decodeBDAddr20Operand()
248 const unsigned *Regs) { in decodeBDXAddr12Operand()
260 const unsigned *Regs) { in decodeBDXAddr20Operand()
272 const unsigned *Regs) { in decodeBDLAddr12Len8Operand()
284 const unsigned *Regs) { in decodeBDVAddr12Operand()
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| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 331 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
358 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
372 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
399 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
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| /external/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 183 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
321 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables()
444 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping()
790 const auto &Regs = RegBank.getRegisters(); in runMCDesc() local
1325 const auto &Regs = RegBank.getRegisters(); in runTargetDesc() local
1423 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc() local
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| D | CodeGenRegisters.cpp | 160 RegUnitIterator(const CodeGenRegister::Vec &Regs): in RegUnitIterator()
940 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); in CodeGenRegBank() local
1298 CodeGenRegister::Vec Regs; member
1327 const CodeGenRegister::Vec &Regs = RegClass.getMembers(); in computeUberSets() local
2087 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) { in computeCoveredRegisters()
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| D | CodeGenTarget.cpp | 235 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); in getRegisterByName() local
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.cpp | 90 static const unsigned Regs[2][2] = { in getFrameRegister() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 971 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple()
980 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple()
989 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple()
1027 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, in SelectTable() local
1194 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStore() local
1212 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStore() local
1266 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectLoadLane() local
1306 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostLoadLane() local
1362 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStoreLane() local
1392 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStoreLane() local
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| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 541 const unsigned *Regs, bool IsAddress) { in parseRegister()
558 const unsigned *Regs, RegisterKind Kind) { in parseRegister()
577 const MCExpr *&Length, const unsigned *Regs, in parseAddress()
638 const unsigned *Regs, RegisterKind RegKind) { in parseAddress()
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DbgValueHistoryCalculator.cpp | 171 BitVector &Regs) { in collectChangingRegs()
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| /external/llvm/lib/CodeGen/ |
| D | CallingConvLower.cpp | 193 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, in getRemainingRegParmsForType()
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| D | AggressiveAntiDepBreaker.cpp | 70 std::vector<unsigned> &Regs, in GetGroupRegs()
544 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
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| D | ExecutionDepsFix.cpp | 648 SmallVector<LiveReg, 4> Regs; in visitSoftInstr() local
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| D | RegisterPressure.cpp | 484 void RegPressureTracker::addLiveRegs(ArrayRef<unsigned> Regs) { in addLiveRegs()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 566 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs, in ContainsReg()
580 DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs) { in CreateLoadStoreMulti()
800 SmallVector<std::pair<unsigned, bool>, 8> Regs; in MergeOpsUpdate() local
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| D | ARMFrameLowering.cpp | 901 SmallVector<std::pair<unsigned,bool>, 4> Regs; in emitPushInst() local
987 SmallVector<unsigned, 4> Regs; in emitPopInst() local
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| D | Thumb2SizeReduction.cpp | 221 for (const MCPhysReg *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) in HasImplicitCPSRDef() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1184 static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) { in dump_registers()
1436 BitVector Regs(Hexagon::NUM_TARGET_REGS); in shouldInlineCSR() local
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| D | HexagonGenInsert.cpp | 961 RegisterSet Regs[2]; in findRemovableRegisters() local
1448 SmallVector<unsigned,2> Regs; in removeDeadCode() local
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| /external/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 926 SmallPtrSetImpl<const SCEV *> &Regs, in RateRegister()
974 SmallPtrSetImpl<const SCEV *> &Regs, in RatePrimaryRegister()
991 SmallPtrSetImpl<const SCEV *> &Regs, in RateFormula()
1248 SmallPtrSet<const SCEV *, 4> Regs; member in __anondd02b9d70711::LSRUse
3864 SmallPtrSet<const SCEV *, 16> Regs; in FilterOutUndesirableDedicatedRegisters() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.h | 919 SmallVector<unsigned, 4> Regs; member
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 2009 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, in DecodeRegListOperand() local
2037 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; in DecodeRegListOperand16() local
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 1242 CreateRegList(SmallVectorImpl<unsigned> &Regs, SMLoc StartLoc, SMLoc EndLoc, in CreateRegList()
4484 SmallVector<unsigned, 10> Regs; in parseRegisterList() local
4587 SmallVector<unsigned, 10> Regs; in parseMovePRegPair() local
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 668 SDValue Regs[2]; in selectBDVAddr12Only() local
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| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 2435 unsigned Regs[2]; in adjustStackWithPops() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 739 SmallVector<SDValue, 4> Regs; in LowerFormalArguments() local
|