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Searched refs:FMA (Results 1 – 25 of 59) sorted by relevance

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/external/llvm/test/CodeGen/X86/
Dfma_patterns.ll2 …own-unknown -mattr=+avx,+fma -fp-contract=fast | FileCheck %s --check-prefix=ALL --check-prefix=FMA
12 ; FMA-LABEL: test_f32_fmadd:
13 ; FMA: # BB#0:
14 ; FMA-NEXT: vfmadd213ss %xmm2, %xmm1, %xmm0
15 ; FMA-NEXT: retq
33 ; FMA-LABEL: test_4f32_fmadd:
34 ; FMA: # BB#0:
35 ; FMA-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0
36 ; FMA-NEXT: retq
53 ; FMA-LABEL: test_8f32_fmadd:
[all …]
Dfma_patterns_wide.ll2 …mtriple=x86_64-unknown-unknown -mattr=+avx,+fma -fp-contract=fast | FileCheck %s --check-prefix=FMA
12 ; FMA-LABEL: test_16f32_fmadd:
13 ; FMA: # BB#0:
14 ; FMA-NEXT: vfmadd213ps %ymm4, %ymm2, %ymm0
15 ; FMA-NEXT: vfmadd213ps %ymm5, %ymm3, %ymm1
16 ; FMA-NEXT: retq
34 ; FMA-LABEL: test_8f64_fmadd:
35 ; FMA: # BB#0:
36 ; FMA-NEXT: vfmadd213pd %ymm4, %ymm2, %ymm0
37 ; FMA-NEXT: vfmadd213pd %ymm5, %ymm3, %ymm1
[all …]
Dfma-intrinsics-x86.ll1 …ch=x86-64 -mcpu=corei7-avx -mattr=+fma | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA
2 …6-64 -mcpu=core-avx2 -mattr=+fma,+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA
3 … -mcpu=core-avx2 -mattr=+fma,+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-WIN
6 …nown-unknown -mcpu=bdver2 -mattr=-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA
13 ; CHECK-FMA-WIN-NEXT: vmovaps {{\(%rcx\), %xmm0|\(%r8\), %xmm1}}
14 ; CHECK-FMA-WIN-NEXT: vmovaps {{\(%rcx\), %xmm0|\(%r8\), %xmm1}}
15 ; CHECK-FMA-WIN-NEXT: vfmadd132ss (%rdx), %xmm1, %xmm0
17 ; CHECK-FMA-NEXT: vfmadd213ss %xmm2, %xmm1, %xmm0
30 ; CHECK-FMA-WIN-NEXT: vmovaps {{\(%rdx\), %xmm0|\(%r8\), %xmm1}}
31 ; CHECK-FMA-WIN-NEXT: vmovaps {{\(%rdx\), %xmm0|\(%r8\), %xmm1}}
[all …]
Dfma.ll1 …pple-darwin10 -mattr=+fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-INST
2 …pple-darwin10 -mattr=-fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-CALL
3 …-apple-darwin10 -mattr=+fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-INST
4 …apple-darwin10 -mattr=-fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-CALL
5 …win10 -mattr=+avx512f,-fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-INST
6 …ch=x86 -mcpu=bdver2 -mattr=-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-INST
7 …86 -mcpu=bdver2 -mattr=-fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-CALL
10 ; CHECK-FMA-INST: vfmadd213ss
11 ; CHECK-FMA-CALL: fmaf
19 ; CHECK-FMA-INST: vfmadd213sd
[all …]
Dfma-do-not-commute.ll8 ; %arg lives in xmm0 and it shouldn't be redefined until it is used in the FMA.
/external/llvm/test/CodeGen/NVPTX/
Dfma-disable.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA
3 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA
8 ; FMA: fma.rn.f32
18 ; FMA: fma.rn.f64
/external/llvm/lib/Target/X86/
DX86InstrFMA.td1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
10 // This file describes FMA (Fused Multiply-Add) instructions.
18 // For all FMA opcodes declared in fma3p_rm and fma3s_rm milticlasses defined
24 // FMA*213*:
28 // FMA*132*:
32 // FMA*231*:
133 // All source register operands of FMA opcodes defined in fma3s_rm multiclass
135 // adjustment, for example, commuting the operands 1 and 2 in FMA*132 form
136 // would require an opcode change to FMA*231:
137 // FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2;
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dfma.ll14 ; EG: FMA {{\*? *}}[[RES]]
30 ; EG-DAG: FMA {{\*? *}}[[RES]].[[CHLO]]
31 ; EG-DAG: FMA {{\*? *}}[[RES]].[[CHHI]]
49 ; EG-DAG: FMA {{\*? *}}[[RES]].X
50 ; EG-DAG: FMA {{\*? *}}[[RES]].Y
51 ; EG-DAG: FMA {{\*? *}}[[RES]].Z
52 ; EG-DAG: FMA {{\*? *}}[[RES]].W
Dfp_to_sint.f64.ll45 ; CI-DAG: v_fma_f64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]{{\]}}, [[TRUNC]]
46 ; CI-DAG: v_cvt_u32_f64_e32 v[[LO:[0-9]+]], [[FMA]]
Dfp_to_uint.f64.ll45 ; CI-DAG: v_fma_f64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]{{\]}}, [[TRUNC]]
46 ; CI-DAG: v_cvt_u32_f64_e32 v[[LO:[0-9]+]], [[FMA]]
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILEvergreenDevice.cpp133 mHWBits.set(AMDGPUDeviceInfo::FMA); in setCaps()
147 mSWBits.set(AMDGPUDeviceInfo::FMA); in setCaps()
164 mSWBits.set(AMDGPUDeviceInfo::FMA); in setCaps()
DAMDILDeviceInfo.h46 FMA = 0xC, // Use HW FMA or SW FMA. enumerator
DAMDILNIDevice.cpp65 mHWBits.set(AMDGPUDeviceInfo::FMA); in setCaps()
DAMDIL7XXDevice.cpp104 mSWBits.set(AMDGPUDeviceInfo::FMA); in setCaps()
/external/llvm/test/CodeGen/PowerPC/
Dfma-mutate.ll1 ; Test several VSX FMA mutation opportunities. The first one isn't a
3 ; same as the FMA target register. The second one is legal. The third
Dvsx-fma-sp.ll91 ; Note: We could convert this next FMA to M-type as well, but it would require
138 ; Note: We could convert this next FMA to M-type as well, but it would require
Dvsx-fma-m.ll98 ; Note: We could convert this next FMA to M-type as well, but it would require
145 ; Note: We could convert this next FMA to M-type as well, but it would require
270 ; Note: We could convert this next FMA to M-type as well, but it would require
322 ; Note: We could convert this next FMA to M-type as well, but it would require
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h244 FMA, enumerator
DBasicTTIImpl.h675 ISD = ISD::FMA; in getIntrinsicInstrCost()
678 ISD = ISD::FMA; in getIntrinsicInstrCost()
/external/llvm/test/tools/llvm-readobj/ARM/
Dattribute-2.s37 @CHECK-OBJ-NEXT: Description: NEONv2+FMA
/external/llvm/lib/Target/AMDGPU/
DAMDGPUInstrInfo.td155 // Special case divide FMA with scale and flags (src0 = Quotient,
DSIISelLowering.cpp1509 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One); in LowerFDIV64()
1511 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp); in LowerFDIV64()
1513 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One); in LowerFDIV64()
1517 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1); in LowerFDIV64()
1520 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64, in LowerFDIV64()
/external/valgrind/docs/internals/
D3_10_BUGSTATUS.txt8 XOP/FMA -- should take, but not before 3.11 release
/external/llvm/lib/Target/PowerPC/
DPPCScheduleP7.td69 // FMA from the VSUs can forward results in 6 cycles. VS1 XS and vector FP
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp200 case ISD::FMA: return "fma"; in getOperationName()

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