/external/llvm/test/CodeGen/X86/ |
D | fma_patterns.ll | 2 …own-unknown -mattr=+avx,+fma -fp-contract=fast | FileCheck %s --check-prefix=ALL --check-prefix=FMA 12 ; FMA-LABEL: test_f32_fmadd: 13 ; FMA: # BB#0: 14 ; FMA-NEXT: vfmadd213ss %xmm2, %xmm1, %xmm0 15 ; FMA-NEXT: retq 33 ; FMA-LABEL: test_4f32_fmadd: 34 ; FMA: # BB#0: 35 ; FMA-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0 36 ; FMA-NEXT: retq 53 ; FMA-LABEL: test_8f32_fmadd: [all …]
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D | fma_patterns_wide.ll | 2 …mtriple=x86_64-unknown-unknown -mattr=+avx,+fma -fp-contract=fast | FileCheck %s --check-prefix=FMA 12 ; FMA-LABEL: test_16f32_fmadd: 13 ; FMA: # BB#0: 14 ; FMA-NEXT: vfmadd213ps %ymm4, %ymm2, %ymm0 15 ; FMA-NEXT: vfmadd213ps %ymm5, %ymm3, %ymm1 16 ; FMA-NEXT: retq 34 ; FMA-LABEL: test_8f64_fmadd: 35 ; FMA: # BB#0: 36 ; FMA-NEXT: vfmadd213pd %ymm4, %ymm2, %ymm0 37 ; FMA-NEXT: vfmadd213pd %ymm5, %ymm3, %ymm1 [all …]
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D | fma-intrinsics-x86.ll | 1 …ch=x86-64 -mcpu=corei7-avx -mattr=+fma | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA 2 …6-64 -mcpu=core-avx2 -mattr=+fma,+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA 3 … -mcpu=core-avx2 -mattr=+fma,+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-WIN 6 …nown-unknown -mcpu=bdver2 -mattr=-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA 13 ; CHECK-FMA-WIN-NEXT: vmovaps {{\(%rcx\), %xmm0|\(%r8\), %xmm1}} 14 ; CHECK-FMA-WIN-NEXT: vmovaps {{\(%rcx\), %xmm0|\(%r8\), %xmm1}} 15 ; CHECK-FMA-WIN-NEXT: vfmadd132ss (%rdx), %xmm1, %xmm0 17 ; CHECK-FMA-NEXT: vfmadd213ss %xmm2, %xmm1, %xmm0 30 ; CHECK-FMA-WIN-NEXT: vmovaps {{\(%rdx\), %xmm0|\(%r8\), %xmm1}} 31 ; CHECK-FMA-WIN-NEXT: vmovaps {{\(%rdx\), %xmm0|\(%r8\), %xmm1}} [all …]
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D | fma.ll | 1 …pple-darwin10 -mattr=+fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-INST 2 …pple-darwin10 -mattr=-fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-CALL 3 …-apple-darwin10 -mattr=+fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-INST 4 …apple-darwin10 -mattr=-fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-CALL 5 …win10 -mattr=+avx512f,-fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-INST 6 …ch=x86 -mcpu=bdver2 -mattr=-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-INST 7 …86 -mcpu=bdver2 -mattr=-fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-CALL 10 ; CHECK-FMA-INST: vfmadd213ss 11 ; CHECK-FMA-CALL: fmaf 19 ; CHECK-FMA-INST: vfmadd213sd [all …]
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D | fma-do-not-commute.ll | 8 ; %arg lives in xmm0 and it shouldn't be redefined until it is used in the FMA.
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/external/llvm/test/CodeGen/NVPTX/ |
D | fma-disable.ll | 1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA 3 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA 8 ; FMA: fma.rn.f32 18 ; FMA: fma.rn.f64
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/external/llvm/lib/Target/X86/ |
D | X86InstrFMA.td | 1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===// 10 // This file describes FMA (Fused Multiply-Add) instructions. 18 // For all FMA opcodes declared in fma3p_rm and fma3s_rm milticlasses defined 24 // FMA*213*: 28 // FMA*132*: 32 // FMA*231*: 133 // All source register operands of FMA opcodes defined in fma3s_rm multiclass 135 // adjustment, for example, commuting the operands 1 and 2 in FMA*132 form 136 // would require an opcode change to FMA*231: 137 // FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2; [all …]
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/external/llvm/test/CodeGen/AMDGPU/ |
D | fma.ll | 14 ; EG: FMA {{\*? *}}[[RES]] 30 ; EG-DAG: FMA {{\*? *}}[[RES]].[[CHLO]] 31 ; EG-DAG: FMA {{\*? *}}[[RES]].[[CHHI]] 49 ; EG-DAG: FMA {{\*? *}}[[RES]].X 50 ; EG-DAG: FMA {{\*? *}}[[RES]].Y 51 ; EG-DAG: FMA {{\*? *}}[[RES]].Z 52 ; EG-DAG: FMA {{\*? *}}[[RES]].W
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D | fp_to_sint.f64.ll | 45 ; CI-DAG: v_fma_f64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]{{\]}}, [[TRUNC]] 46 ; CI-DAG: v_cvt_u32_f64_e32 v[[LO:[0-9]+]], [[FMA]]
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D | fp_to_uint.f64.ll | 45 ; CI-DAG: v_fma_f64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]{{\]}}, [[TRUNC]] 46 ; CI-DAG: v_cvt_u32_f64_e32 v[[LO:[0-9]+]], [[FMA]]
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/external/mesa3d/src/gallium/drivers/radeon/ |
D | AMDILEvergreenDevice.cpp | 133 mHWBits.set(AMDGPUDeviceInfo::FMA); in setCaps() 147 mSWBits.set(AMDGPUDeviceInfo::FMA); in setCaps() 164 mSWBits.set(AMDGPUDeviceInfo::FMA); in setCaps()
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D | AMDILDeviceInfo.h | 46 FMA = 0xC, // Use HW FMA or SW FMA. enumerator
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D | AMDILNIDevice.cpp | 65 mHWBits.set(AMDGPUDeviceInfo::FMA); in setCaps()
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D | AMDIL7XXDevice.cpp | 104 mSWBits.set(AMDGPUDeviceInfo::FMA); in setCaps()
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/external/llvm/test/CodeGen/PowerPC/ |
D | fma-mutate.ll | 1 ; Test several VSX FMA mutation opportunities. The first one isn't a 3 ; same as the FMA target register. The second one is legal. The third
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D | vsx-fma-sp.ll | 91 ; Note: We could convert this next FMA to M-type as well, but it would require 138 ; Note: We could convert this next FMA to M-type as well, but it would require
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D | vsx-fma-m.ll | 98 ; Note: We could convert this next FMA to M-type as well, but it would require 145 ; Note: We could convert this next FMA to M-type as well, but it would require 270 ; Note: We could convert this next FMA to M-type as well, but it would require 322 ; Note: We could convert this next FMA to M-type as well, but it would require
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/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 244 FMA, enumerator
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D | BasicTTIImpl.h | 675 ISD = ISD::FMA; in getIntrinsicInstrCost() 678 ISD = ISD::FMA; in getIntrinsicInstrCost()
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/external/llvm/test/tools/llvm-readobj/ARM/ |
D | attribute-2.s | 37 @CHECK-OBJ-NEXT: Description: NEONv2+FMA
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/external/llvm/lib/Target/AMDGPU/ |
D | AMDGPUInstrInfo.td | 155 // Special case divide FMA with scale and flags (src0 = Quotient,
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D | SIISelLowering.cpp | 1509 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One); in LowerFDIV64() 1511 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp); in LowerFDIV64() 1513 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One); in LowerFDIV64() 1517 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1); in LowerFDIV64() 1520 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64, in LowerFDIV64()
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/external/valgrind/docs/internals/ |
D | 3_10_BUGSTATUS.txt | 8 XOP/FMA -- should take, but not before 3.11 release
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/external/llvm/lib/Target/PowerPC/ |
D | PPCScheduleP7.td | 69 // FMA from the VSUs can forward results in 6 cycles. VS1 XS and vector FP
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGDumper.cpp | 200 case ISD::FMA: return "fma"; in getOperationName()
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