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/external/valgrind/none/tests/ppc64/
Dtest_dfp3.c34 register double f18 __asm__ ("fr18");
91 __asm__ __volatile__ ("drintx 1, %0, %1, 0" : "=f" (f18) : "f" (f16)); in _test_drintx()
93 __asm__ __volatile__ ("drintx 0, %0, %1, 0" : "=f" (f18) : "f" (f16)); in _test_drintx()
97 __asm__ __volatile__ ("drintx 1, %0, %1, 1" : "=f" (f18) : "f" (f16)); in _test_drintx()
99 __asm__ __volatile__ ("drintx 0, %0, %1, 1" : "=f" (f18) : "f" (f16)); in _test_drintx()
103 __asm__ __volatile__ ("drintx 1, %0, %1, 2" : "=f" (f18) : "f" (f16)); in _test_drintx()
105 __asm__ __volatile__ ("drintx 0, %0, %1, 2" : "=f" (f18) : "f" (f16)); in _test_drintx()
109 __asm__ __volatile__ ("drintx 1, %0, %1, 3" : "=f" (f18) : "f" (f16)); in _test_drintx()
111 __asm__ __volatile__ ("drintx 0, %0, %1, 3" : "=f" (f18) : "f" (f16)); in _test_drintx()
127 __asm__ __volatile__ ("drintn 1, %0, %1, 0" : "=f" (f18) : "f" (f16)); in _test_drintn()
[all …]
Dtest_dfp2.c39 register double f18 __asm__ ("fr18");
116 __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0)); in _test_dscri()
120 __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1)); in _test_dscri()
124 __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2)); in _test_dscri()
128 __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3)); in _test_dscri()
139 __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0)); in _test_dscli()
143 __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1)); in _test_dscli()
147 __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2)); in _test_dscli()
151 __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3)); in _test_dscli()
160 __asm__ __volatile__ ("dctdp %0, %1" : "=f" (f18) : "f" (f14)); in _test_dctdp()
[all …]
Dtest_dfp1.c33 register double f18 __asm__ ("fr18");
85 __asm__ __volatile__ ("dadd. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dadd()
87 __asm__ __volatile__ ("dadd %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dadd()
93 __asm__ __volatile__ ("dsub. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dsub()
95 __asm__ __volatile__ ("dsub %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dsub()
101 __asm__ __volatile__ ("dmul. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dmul()
103 __asm__ __volatile__ ("dmul %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dmul()
109 __asm__ __volatile__ ("ddiv. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_ddiv()
111 __asm__ __volatile__ ("ddiv %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_ddiv()
118 __asm__ __volatile__ ("daddq. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_daddq()
[all …]
/external/valgrind/none/tests/ppc32/
Dtest_dfp3.c34 register double f18 __asm__ ("fr18");
91 __asm__ __volatile__ ("drintx 1, %0, %1, 0" : "=f" (f18) : "f" (f16)); in _test_drintx()
93 __asm__ __volatile__ ("drintx 0, %0, %1, 0" : "=f" (f18) : "f" (f16)); in _test_drintx()
97 __asm__ __volatile__ ("drintx 1, %0, %1, 1" : "=f" (f18) : "f" (f16)); in _test_drintx()
99 __asm__ __volatile__ ("drintx 0, %0, %1, 1" : "=f" (f18) : "f" (f16)); in _test_drintx()
103 __asm__ __volatile__ ("drintx 1, %0, %1, 2" : "=f" (f18) : "f" (f16)); in _test_drintx()
105 __asm__ __volatile__ ("drintx 0, %0, %1, 2" : "=f" (f18) : "f" (f16)); in _test_drintx()
109 __asm__ __volatile__ ("drintx 1, %0, %1, 3" : "=f" (f18) : "f" (f16)); in _test_drintx()
111 __asm__ __volatile__ ("drintx 0, %0, %1, 3" : "=f" (f18) : "f" (f16)); in _test_drintx()
127 __asm__ __volatile__ ("drintn 1, %0, %1, 0" : "=f" (f18) : "f" (f16)); in _test_drintn()
[all …]
Dtest_dfp2.c39 register double f18 __asm__ ("fr18");
116 __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0)); in _test_dscri()
120 __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1)); in _test_dscri()
124 __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2)); in _test_dscri()
128 __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3)); in _test_dscri()
139 __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0)); in _test_dscli()
143 __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1)); in _test_dscli()
147 __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2)); in _test_dscli()
151 __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3)); in _test_dscli()
160 __asm__ __volatile__ ("dctdp %0, %1" : "=f" (f18) : "f" (f14)); in _test_dctdp()
[all …]
Dtest_dfp1.c33 register double f18 __asm__ ("fr18");
85 __asm__ __volatile__ ("dadd. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dadd()
87 __asm__ __volatile__ ("dadd %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dadd()
93 __asm__ __volatile__ ("dsub. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dsub()
95 __asm__ __volatile__ ("dsub %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dsub()
101 __asm__ __volatile__ ("dmul. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dmul()
103 __asm__ __volatile__ ("dmul %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_dmul()
109 __asm__ __volatile__ ("ddiv. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_ddiv()
111 __asm__ __volatile__ ("ddiv %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_ddiv()
118 __asm__ __volatile__ ("daddq. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); in _test_daddq()
[all …]
/external/llvm/test/MC/Disassembler/Mips/mips64r3/
Dvalid-xfail-mips64r3.txt7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
51 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
57 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
58 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
60 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
61 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
70 0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
/external/llvm/test/MC/Disassembler/Mips/mips64r5/
Dvalid-xfail-mips64r5.txt7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
51 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
57 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
58 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
60 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
61 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
70 0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
/external/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-xfail-mips64r2.txt7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
51 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
57 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
58 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
60 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
61 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
70 0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
/external/llvm/test/MC/Disassembler/Mips/mips4/
Dvalid-xfail-mips4.txt7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
31 0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20
33 0x4c 0x32 0xfa 0xa9 # CHECK: msub.d $f10, $f1, $f31, $f18
35 0x4d 0x33 0x74 0xb1 # CHECK: nmadd.d $f18, $f9, $f14, $f19
/external/llvm/test/MC/Disassembler/Mips/mips64/
Dvalid-mips64-xfail.txt7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
33 0x4d 0x9e 0x93 0x1e # CHECK: alnv.ps $f12, $f18, $f30, $8
50 0x46 0x13 0x90 0xe6 # CHECK: cvt.ps.s $f3, $f18, $f19
53 0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20
60 0x46 0xdf 0x8c 0x92 # CHECK: movz.ps $f18, $f17, ra
61 0x4c 0x32 0xfa 0xa9 # CHECK: msub.d $f10, $f1, $f31, $f18
66 0x4d 0x33 0x74 0xb1 # CHECK: nmadd.d $f18, $f9, $f14, $f19
/external/llvm/test/MC/Disassembler/Mips/mips32r3/
Dvalid-xfail-mips32r3.txt7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
63 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
65 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
73 0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
/external/llvm/test/MC/Disassembler/Mips/mips32r5/
Dvalid-xfail-mips32r5.txt7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
63 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
65 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
73 0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
/external/llvm/test/MC/Disassembler/Mips/mips32r2/
Dvalid-xfail-mips32r2.txt7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
63 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
65 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
73 0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips32r2.s8 …madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
10 …msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
12 …nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips5-wrong-error.s10 … alnv.ps $f12,$f18,$f30,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
31 … cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
32 … cvt.ps.pw $f3,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
38 … movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/external/llvm/test/MC/Mips/mips4/
Dvalid.s49 ceil.l.s $f18,$f13
145 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
146 madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
169 msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
170 msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28]
183 neg.d $f27,$f18
185 nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1]
231 sub.d $f18,$f3,$f17
/external/llvm/test/MC/Mips/mips64/
Dvalid.s49 ceil.l.s $f18,$f13
157 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
158 madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
184 msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
185 msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28]
200 neg.d $f27,$f18
202 nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1]
250 sub.d $f18,$f3,$f17
/external/llvm/test/MC/Mips/mips5/
Dvalid.s49 ceil.l.s $f18,$f13
146 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
147 madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
170 msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
171 msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28]
184 neg.d $f27,$f18
186 nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1]
232 sub.d $f18,$f3,$f17
/external/llvm/test/MC/Disassembler/Mips/mips32/
Dvalid-xfail-mips32.txt7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
/external/llvm/test/CodeGen/PowerPC/
Dvsx-spill.ll10 …{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f2…
31 …{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f2…
51 …{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f2…
/external/valgrind/none/tests/mips32/
DMoveIns.c301 TESTINSNMOVE("mfc1 $a1, $f18", 4, f18, a1); in main()
330 TESTINSNMOVEt("mtc1 $a1, $f18", 6, f18, a1); in main()
359 TESTINSNMOVE1s("mov.s $f17, $f18", 4, f17, f18); in main()
360 TESTINSNMOVE1s("mov.s $f18, $f19", 8, f18, f19); in main()
387 TESTINSNMOVE1d("mov.d $f16, $f18", 64, f16, f18); in main()
388 TESTINSNMOVE1d("mov.d $f16, $f18", 0, f16, f18); in main()
389 TESTINSNMOVE1d("mov.d $f18, $f20", 8, f18, f20); in main()
390 TESTINSNMOVE1d("mov.d $f18, $f20", 16, f18, f20); in main()
/external/llvm/test/MC/Mips/mips3/
Dinvalid-mips5-wrong-error.s11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
28 cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips5-wrong-error.s11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
28 cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips5-wrong-error.s11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
28 cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

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