1 #ifndef _I810_DRM_H_ 2 #define _I810_DRM_H_ 3 4 #include <drm/drm.h> 5 6 /* WARNING: These defines must be the same as what the Xserver uses. 7 * if you change them, you must change the defines in the Xserver. 8 */ 9 10 #ifndef _I810_DEFINES_ 11 #define _I810_DEFINES_ 12 13 #define I810_DMA_BUF_ORDER 12 14 #define I810_DMA_BUF_SZ (1<<I810_DMA_BUF_ORDER) 15 #define I810_DMA_BUF_NR 256 16 #define I810_NR_SAREA_CLIPRECTS 8 17 18 /* Each region is a minimum of 64k, and there are at most 64 of them. 19 */ 20 #define I810_NR_TEX_REGIONS 64 21 #define I810_LOG_MIN_TEX_REGION_SIZE 16 22 #endif 23 24 #define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ 25 #define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ 26 #define I810_UPLOAD_CTX 0x4 27 #define I810_UPLOAD_BUFFERS 0x8 28 #define I810_UPLOAD_TEX0 0x10 29 #define I810_UPLOAD_TEX1 0x20 30 #define I810_UPLOAD_CLIPRECTS 0x40 31 32 /* Indices into buf.Setup where various bits of state are mirrored per 33 * context and per buffer. These can be fired at the card as a unit, 34 * or in a piecewise fashion as required. 35 */ 36 37 /* Destbuffer state 38 * - backbuffer linear offset and pitch -- invarient in the current dri 39 * - zbuffer linear offset and pitch -- also invarient 40 * - drawing origin in back and depth buffers. 41 * 42 * Keep the depth/back buffer state here to accommodate private buffers 43 * in the future. 44 */ 45 #define I810_DESTREG_DI0 0 /* CMD_OP_DESTBUFFER_INFO (2 dwords) */ 46 #define I810_DESTREG_DI1 1 47 #define I810_DESTREG_DV0 2 /* GFX_OP_DESTBUFFER_VARS (2 dwords) */ 48 #define I810_DESTREG_DV1 3 49 #define I810_DESTREG_DR0 4 /* GFX_OP_DRAWRECT_INFO (4 dwords) */ 50 #define I810_DESTREG_DR1 5 51 #define I810_DESTREG_DR2 6 52 #define I810_DESTREG_DR3 7 53 #define I810_DESTREG_DR4 8 54 #define I810_DEST_SETUP_SIZE 10 55 56 /* Context state 57 */ 58 #define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */ 59 #define I810_CTXREG_CF1 1 60 #define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */ 61 #define I810_CTXREG_ST1 3 62 #define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */ 63 #define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */ 64 #define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */ 65 #define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */ 66 #define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */ 67 #define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */ 68 #define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */ 69 #define I810_CTXREG_MA2 11 /* GFX_OP_MAP_ALPHA_STAGES - stage 2 */ 70 #define I810_CTXREG_SDM 12 /* GFX_OP_SRC_DEST_MONO */ 71 #define I810_CTXREG_FOG 13 /* GFX_OP_FOG_COLOR */ 72 #define I810_CTXREG_B1 14 /* GFX_OP_BOOL_1 */ 73 #define I810_CTXREG_B2 15 /* GFX_OP_BOOL_2 */ 74 #define I810_CTXREG_LCS 16 /* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */ 75 #define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */ 76 #define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */ 77 #define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */ 78 #define I810_CTX_SETUP_SIZE 20 79 80 /* Texture state (per tex unit) 81 */ 82 #define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */ 83 #define I810_TEXREG_MI1 1 84 #define I810_TEXREG_MI2 2 85 #define I810_TEXREG_MI3 3 86 #define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */ 87 #define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */ 88 #define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */ 89 #define I810_TEXREG_MCS 7 /* GFX_OP_MAP_COORD_SETS ??? */ 90 #define I810_TEX_SETUP_SIZE 8 91 92 /* Flags for clear ioctl 93 */ 94 #define I810_FRONT 0x1 95 #define I810_BACK 0x2 96 #define I810_DEPTH 0x4 97 98 typedef enum _drm_i810_init_func { 99 I810_INIT_DMA = 0x01, 100 I810_CLEANUP_DMA = 0x02, 101 I810_INIT_DMA_1_4 = 0x03 102 } drm_i810_init_func_t; 103 104 /* This is the init structure after v1.2 */ 105 typedef struct _drm_i810_init { 106 drm_i810_init_func_t func; 107 unsigned int mmio_offset; 108 unsigned int buffers_offset; 109 int sarea_priv_offset; 110 unsigned int ring_start; 111 unsigned int ring_end; 112 unsigned int ring_size; 113 unsigned int front_offset; 114 unsigned int back_offset; 115 unsigned int depth_offset; 116 unsigned int overlay_offset; 117 unsigned int overlay_physical; 118 unsigned int w; 119 unsigned int h; 120 unsigned int pitch; 121 unsigned int pitch_bits; 122 } drm_i810_init_t; 123 124 /* This is the init structure prior to v1.2 */ 125 typedef struct _drm_i810_pre12_init { 126 drm_i810_init_func_t func; 127 unsigned int mmio_offset; 128 unsigned int buffers_offset; 129 int sarea_priv_offset; 130 unsigned int ring_start; 131 unsigned int ring_end; 132 unsigned int ring_size; 133 unsigned int front_offset; 134 unsigned int back_offset; 135 unsigned int depth_offset; 136 unsigned int w; 137 unsigned int h; 138 unsigned int pitch; 139 unsigned int pitch_bits; 140 } drm_i810_pre12_init_t; 141 142 /* Warning: If you change the SAREA structure you must change the Xserver 143 * structure as well */ 144 145 typedef struct _drm_i810_tex_region { 146 unsigned char next, prev; /* indices to form a circular LRU */ 147 unsigned char in_use; /* owned by a client, or free? */ 148 int age; /* tracked by clients to update local LRU's */ 149 } drm_i810_tex_region_t; 150 151 typedef struct _drm_i810_sarea { 152 unsigned int ContextState[I810_CTX_SETUP_SIZE]; 153 unsigned int BufferState[I810_DEST_SETUP_SIZE]; 154 unsigned int TexState[2][I810_TEX_SETUP_SIZE]; 155 unsigned int dirty; 156 157 unsigned int nbox; 158 struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS]; 159 160 /* Maintain an LRU of contiguous regions of texture space. If 161 * you think you own a region of texture memory, and it has an 162 * age different to the one you set, then you are mistaken and 163 * it has been stolen by another client. If global texAge 164 * hasn't changed, there is no need to walk the list. 165 * 166 * These regions can be used as a proxy for the fine-grained 167 * texture information of other clients - by maintaining them 168 * in the same lru which is used to age their own textures, 169 * clients have an approximate lru for the whole of global 170 * texture space, and can make informed decisions as to which 171 * areas to kick out. There is no need to choose whether to 172 * kick out your own texture or someone else's - simply eject 173 * them all in LRU order. 174 */ 175 176 drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1]; 177 /* Last elt is sentinal */ 178 int texAge; /* last time texture was uploaded */ 179 int last_enqueue; /* last time a buffer was enqueued */ 180 int last_dispatch; /* age of the most recently dispatched buffer */ 181 int last_quiescent; /* */ 182 int ctxOwner; /* last context to upload state */ 183 184 int vertex_prim; 185 186 int pf_enabled; /* is pageflipping allowed? */ 187 int pf_active; 188 int pf_current_page; /* which buffer is being displayed? */ 189 } drm_i810_sarea_t; 190 191 /* WARNING: If you change any of these defines, make sure to change the 192 * defines in the Xserver file (xf86drmMga.h) 193 */ 194 195 /* i810 specific ioctls 196 * The device specific ioctl range is 0x40 to 0x79. 197 */ 198 #define DRM_I810_INIT 0x00 199 #define DRM_I810_VERTEX 0x01 200 #define DRM_I810_CLEAR 0x02 201 #define DRM_I810_FLUSH 0x03 202 #define DRM_I810_GETAGE 0x04 203 #define DRM_I810_GETBUF 0x05 204 #define DRM_I810_SWAP 0x06 205 #define DRM_I810_COPY 0x07 206 #define DRM_I810_DOCOPY 0x08 207 #define DRM_I810_OV0INFO 0x09 208 #define DRM_I810_FSTATUS 0x0a 209 #define DRM_I810_OV0FLIP 0x0b 210 #define DRM_I810_MC 0x0c 211 #define DRM_I810_RSTATUS 0x0d 212 #define DRM_I810_FLIP 0x0e 213 214 #define DRM_IOCTL_I810_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t) 215 #define DRM_IOCTL_I810_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t) 216 #define DRM_IOCTL_I810_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t) 217 #define DRM_IOCTL_I810_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_I810_FLUSH) 218 #define DRM_IOCTL_I810_GETAGE DRM_IO( DRM_COMMAND_BASE + DRM_I810_GETAGE) 219 #define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t) 220 #define DRM_IOCTL_I810_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_I810_SWAP) 221 #define DRM_IOCTL_I810_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t) 222 #define DRM_IOCTL_I810_DOCOPY DRM_IO( DRM_COMMAND_BASE + DRM_I810_DOCOPY) 223 #define DRM_IOCTL_I810_OV0INFO DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t) 224 #define DRM_IOCTL_I810_FSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS) 225 #define DRM_IOCTL_I810_OV0FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP) 226 #define DRM_IOCTL_I810_MC DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t) 227 #define DRM_IOCTL_I810_RSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS) 228 #define DRM_IOCTL_I810_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP) 229 230 typedef struct _drm_i810_clear { 231 int clear_color; 232 int clear_depth; 233 int flags; 234 } drm_i810_clear_t; 235 236 /* These may be placeholders if we have more cliprects than 237 * I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to 238 * false, indicating that the buffer will be dispatched again with a 239 * new set of cliprects. 240 */ 241 typedef struct _drm_i810_vertex { 242 int idx; /* buffer index */ 243 int used; /* nr bytes in use */ 244 int discard; /* client is finished with the buffer? */ 245 } drm_i810_vertex_t; 246 247 typedef struct _drm_i810_copy_t { 248 int idx; /* buffer index */ 249 int used; /* nr bytes in use */ 250 void *address; /* Address to copy from */ 251 } drm_i810_copy_t; 252 253 #define PR_TRIANGLES (0x0<<18) 254 #define PR_TRISTRIP_0 (0x1<<18) 255 #define PR_TRISTRIP_1 (0x2<<18) 256 #define PR_TRIFAN (0x3<<18) 257 #define PR_POLYGON (0x4<<18) 258 #define PR_LINES (0x5<<18) 259 #define PR_LINESTRIP (0x6<<18) 260 #define PR_RECTS (0x7<<18) 261 #define PR_MASK (0x7<<18) 262 263 typedef struct drm_i810_dma { 264 void *virtual; 265 int request_idx; 266 int request_size; 267 int granted; 268 } drm_i810_dma_t; 269 270 typedef struct _drm_i810_overlay_t { 271 unsigned int offset; /* Address of the Overlay Regs */ 272 unsigned int physical; 273 } drm_i810_overlay_t; 274 275 typedef struct _drm_i810_mc { 276 int idx; /* buffer index */ 277 int used; /* nr bytes in use */ 278 int num_blocks; /* number of GFXBlocks */ 279 int *length; /* List of lengths for GFXBlocks (FUTURE) */ 280 unsigned int last_render; /* Last Render Request */ 281 } drm_i810_mc_t; 282 283 #endif /* _I810_DRM_H_ */ 284