| /external/llvm/lib/Target/Lanai/ |
| D | LanaiCondCode.h | 10 enum CondCode { enum
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| D | LanaiInstrInfo.cpp | 525 unsigned CondCode = MI.getOperand(3).getImm(); in optimizeSelect() local
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/InstPrinter/ |
| D | MipsInstPrinter.h | 33 enum CondCode { enum
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| /external/llvm/lib/Target/Mips/InstPrinter/ |
| D | MipsInstPrinter.h | 33 enum CondCode { enum
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrInfo.h | 32 enum CondCode { enum
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| D | X86ISelLowering.cpp | 8649 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); in LowerSELECT() local
8730 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); in LowerSELECT() local
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 33 enum CondCode { enum
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| D | X86ISelLowering.cpp | 15836 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); in LowerSELECT() local
15964 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); in LowerSELECT() local
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.h | 39 enum CondCode { enum
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| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| D | XCoreInstrInfo.cpp | 32 enum CondCode { enum
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.cpp | 38 enum CondCode { enum
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| /external/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 1030 LPCC::CondCode CondCode = in splitMnemonic() local
1050 LPCC::CondCode CondCode = LPCC::suffixToLanaiCondCode(Mnemonic); in splitMnemonic() local
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 193 enum CondCode { // Meaning (integer) Meaning (floating-point) enum
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 712 enum CondCode { enum
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 1059 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); in Select() local
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 850 enum CondCode { enum
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1029 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, in FPCCToARMCC()
2689 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); in getARMCmp() local
2801 ARMCC::CondCodes CondCode, CondCode2; in LowerSELECT_CC() local
2925 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); in OptimizeVFPBrcond() local
2961 ARMCC::CondCodes CondCode, CondCode2; in LowerBR_CC() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1346 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, in FPCCToARMCC()
3462 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); in getARMCmp() local
3648 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode, in checkVSELConstraints()
3892 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); in LowerSELECT_CC() local
3906 ARMCC::CondCodes CondCode, CondCode2; in LowerSELECT_CC() local
4050 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); in OptimizeVFPBrcond() local
4097 ARMCC::CondCodes CondCode, CondCode2; in LowerBR_CC() local
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| D | ARMBaseInstrInfo.cpp | 1917 unsigned CondCode = MI.getOperand(3).getImm(); in optimizeSelect() local
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir.h | 168 enum CondCode enum
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 986 unsigned CondCode = MI.getOperand(3).getImm(); in EmitF128CSEL() local
1079 AArch64CC::CondCode &CondCode, in changeFPCCToAArch64CC()
1142 AArch64CC::CondCode &CondCode, in changeFPCCToANDAArch64CC()
1172 AArch64CC::CondCode &CondCode, in changeVectorFPCCToAArch64CC()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 1005 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get(); in performVSELECTCombine() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2969 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); in Select() local
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 257 struct CondCodeOp CondCode; member
|