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Searched defs:VT (Results 1 – 25 of 229) sorted by relevance

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/external/llvm/lib/Target/X86/Utils/
DX86ShuffleDecode.cpp48 void DecodeInsertElementMask(MVT VT, unsigned Idx, unsigned Len, in DecodeInsertElementMask()
77 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVSLDUPMask()
85 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVSHDUPMask()
93 void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVDDUPMask()
107 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSLLDQMask()
121 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSRLDQMask()
136 void DecodePALIGNRMask(MVT VT, unsigned Imm, in DecodePALIGNRMask()
157 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSHUFMask()
174 void DecodePSHUFHWMask(MVT VT, unsigned Imm, in DecodePSHUFHWMask()
190 void DecodePSHUFLWMask(MVT VT, unsigned Imm, in DecodePSHUFLWMask()
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/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetLowering.h202 virtual TargetRegisterClass *getRegClassFor(EVT VT) const { in getRegClassFor()
214 virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const { in getRepRegClassFor()
222 virtual uint8_t getRepRegClassCostFor(EVT VT) const { in getRepRegClassCostFor()
230 bool isTypeLegal(EVT VT) const { in isTypeLegal()
246 LegalizeTypeAction getTypeAction(MVT VT) const { in getTypeAction()
250 void setTypeAction(EVT VT, LegalizeTypeAction Action) { in setTypeAction()
264 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const { in getTypeAction()
267 LegalizeTypeAction getTypeAction(MVT VT) const { in getTypeAction()
277 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { in getTypeToTransformTo()
285 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { in getTypeToExpandTo()
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/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp402 MVT VT = Op.getSimpleValueType(); in Promote() local
435 EVT VT = Op.getOperand(0).getValueType(); in PromoteINT_TO_FP() local
471 EVT VT = Op.getValueType(); in PromoteFP_TO_INT() local
713 EVT VT = Op.getValueType(); in ExpandSELECT() local
768 EVT VT = Op.getValueType(); in ExpandSEXTINREG() local
791 EVT VT = Op.getValueType(); in ExpandANY_EXTEND_VECTOR_INREG() local
814 EVT VT = Op.getValueType(); in ExpandSIGN_EXTEND_VECTOR_INREG() local
838 EVT VT = Op.getValueType(); in ExpandZERO_EXTEND_VECTOR_INREG() local
863 static void createBSWAPShuffleMask(EVT VT, SmallVectorImpl<int> &ShuffleMask) { in createBSWAPShuffleMask()
871 EVT VT = Op.getValueType(); in ExpandBSWAP() local
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DLegalizeTypes.h63 TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const { in getTypeAction()
68 bool isTypeLegal(EVT VT) const { in isTypeLegal()
73 bool isSimpleLegalType(EVT VT) const { in isSimpleLegalType()
81 bool isLegalInHWReg(EVT VT) const { in isLegalInHWReg()
86 EVT getSetCCResultType(EVT VT) const { in getSetCCResultType()
DSelectionDAG.cpp79 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType()
679 EVT VT = N->getValueType(0); in VerifySDNode() local
754 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
1001 SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getAnyExtOrTrunc()
1007 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getSExtOrTrunc()
1013 SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getZExtOrTrunc()
1019 SDValue SelectionDAG::getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, in getBoolExtOrTrunc()
1028 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) { in getZeroExtendInReg()
1041 EVT VT) { in getAnyExtendVectorInReg()
1052 EVT VT) { in getSignExtendVectorInReg()
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DDAGCombiner.cpp503 bool isTypeLegal(const EVT &VT) { in isTypeLegal()
818 EVT VT = N0.getValueType(); in ReassociateOps() local
939 EVT VT = Load->getValueType(0); in ReplaceLoadWithPromotedLoad() local
1031 EVT VT = Op.getValueType(); in PromoteIntBinOp() local
1089 EVT VT = Op.getValueType(); in PromoteIntShiftOp() local
1133 EVT VT = Op.getValueType(); in PromoteExtend() local
1165 EVT VT = Op.getValueType(); in PromoteLoad() local
1636 EVT VT = N0.getValueType(); in visitADD() local
1783 EVT VT = N0.getValueType(); in visitADDC() local
1842 static SDValue tryFoldToZero(const SDLoc &DL, const TargetLowering &TLI, EVT VT, in tryFoldToZero()
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DResourcePriorityQueue.cpp96 MVT VT = ScegN->getSimpleValueType(i); in numberRCValPredInSU() local
134 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU() local
334 MVT VT = SU->getNode()->getSimpleValueType(i); in rawRegPressureDelta() local
343 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in rawRegPressureDelta() local
486 MVT VT = ScegN->getSimpleValueType(i); in scheduledNode() local
497 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in scheduledNode() local
/external/llvm/include/llvm/Target/
DTargetLowering.h210 getPreferredVectorAction(EVT VT) const { in getPreferredVectorAction()
237 virtual bool isIntDivCheap(EVT VT, AttributeSet Attr) const { in isIntDivCheap()
323 virtual bool hasBitPreservingFPLogic(EVT VT) const { in hasBitPreservingFPLogic()
379 virtual bool enableAggressiveFMAFusion(EVT VT) const { in enableAggressiveFMAFusion()
430 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { in getRegClassFor()
443 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { in getRepRegClassFor()
450 virtual uint8_t getRepRegClassCostFor(MVT VT) const { in getRepRegClassCostFor()
457 bool isTypeLegal(EVT VT) const { in isTypeLegal()
474 LegalizeTypeAction getTypeAction(MVT VT) const { in getTypeAction()
478 void setTypeAction(MVT VT, LegalizeTypeAction Action) { in setTypeAction()
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/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86FastISel.cpp148 bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) { in isTypeLegal()
176 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, in X86FastEmitLoad()
235 X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM) { in X86FastEmitStore()
268 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val, in X86FastEmitStore()
677 MVT VT; in X86SelectStore() local
803 MVT VT; in X86SelectLoad() local
819 static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) { in X86ChooseCmpOpcode()
840 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) { in X86ChooseCmpImmediateOpcode()
857 EVT VT) { in X86FastEmitCompare()
892 MVT VT; in X86SelectCmp() local
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DX86ISelLowering.cpp84 EVT VT = Vec.getValueType(); in Extract128BitVector() local
128 EVT VT = Vec.getValueType(); in Insert128BitVector() local
352 MVT VT = IntVTs[i]; in X86TargetLowering() local
477 MVT VT = IntVTs[i]; in X86TargetLowering() local
684 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; in X86TargetLowering() local
852 EVT VT = (MVT::SimpleValueType)i; in X86TargetLowering() local
882 EVT VT = SVT; in X86TargetLowering() local
1057 EVT VT = SVT; in X86TargetLowering() local
1079 EVT VT = SVT; in X86TargetLowering() local
1100 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; in X86TargetLowering() local
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/external/llvm/lib/CodeGen/
DCallingConvLower.cpp93 MVT VT = Outs[i].VT; in CheckReturn() local
107 MVT VT = Outs[i].VT; in AnalyzeReturn() local
160 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
173 void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { in AnalyzeCallResult()
183 static bool isValueTypeInRegForCC(CallingConv::ID CC, MVT VT) { in isValueTypeInRegForCC()
194 MVT VT, CCAssignFn Fn) { in getRemainingRegParmsForType()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp298 bool isTypeLegal(const EVT &VT) { in isTypeLegal()
533 EVT VT = N0.getValueType(); in ReassociateOps() local
666 EVT VT = Load->getValueType(0); in ReplaceLoadWithPromotedLoad() local
761 EVT VT = Op.getValueType(); in PromoteIntBinOp() local
819 EVT VT = Op.getValueType(); in PromoteIntShiftOp() local
863 EVT VT = Op.getValueType(); in PromoteExtend() local
892 EVT VT = Op.getValueType(); in PromoteLoad() local
1296 EVT VT = N0.getValueType(); in combineShlAddConstant() local
1320 EVT VT = N0.getValueType(); in visitADD() local
1486 EVT VT = N0.getValueType(); in visitADDC() local
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DSelectionDAG.cpp63 static const fltSemantics *EVTToAPFloatSemantics(EVT VT) { in EVTToAPFloatSemantics()
88 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType()
633 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
755 EVT VT = N->getValueType(0); in VerifyNodeCommon() local
884 SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, DebugLoc DL, EVT VT) { in getAnyExtOrTrunc()
890 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, DebugLoc DL, EVT VT) { in getSExtOrTrunc()
896 SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, DebugLoc DL, EVT VT) { in getZExtOrTrunc()
902 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, EVT VT) { in getZeroExtendInReg()
916 SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, EVT VT) { in getNOT()
923 SDValue SelectionDAG::getConstant(uint64_t Val, EVT VT, bool isT) { in getConstant()
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DLegalizeVectorOps.cpp246 EVT VT = Op.getValueType(); in PromoteVectorOp() local
268 EVT VT = Op.getOperand(0).getValueType(); in ExpandVSELECT() local
300 EVT VT = Op.getOperand(0).getValueType(); in ExpandUINT_TO_FLOAT() local
349 EVT VT = Op.getValueType(); in UnrollVSETCC() local
DLegalizeDAG.cpp165 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, in ShuffleWithNarrowerEltType()
346 EVT VT = CFP->getValueType(0); in ExpandConstantFP() local
389 EVT VT = Val.getValueType(); in ExpandUnalignedStore() local
500 EVT VT = LD->getValueType(0); in ExpandUnalignedLoad() local
650 EVT VT = Tmp1.getValueType(); in PerformInsertVectorEltInMemory() local
996 EVT VT = Node->getValueType(0); in LegalizeOp() local
1135 EVT VT = Node->getValueType(0); in LegalizeOp() local
1508 EVT VT = Tmp3.getValueType(); in LegalizeOp() local
1837 EVT VT = Node->getValueType(0); in ExpandVectorBuildThroughStack() local
1949 EVT VT = Node->getValueType(0); in ExpandDYNAMIC_STACKALLOC() local
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/external/swiftshader/third_party/LLVM/lib/CodeGen/
DCallingConvLower.cpp92 MVT VT = Outs[i].VT; in CheckReturn() local
106 MVT VT = Outs[i].VT; in AnalyzeReturn() local
160 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
174 void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { in AnalyzeCallResult()
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.h47 EVT VT) const override { in isShuffleMaskLegal()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp49 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType()
58 EVT AMDGPUTargetLowering::getEquivalentBitType(LLVMContext &Ctx, EVT VT) { in getEquivalentBitType()
100 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
106 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
126 for (MVT VT : MVT::integer_vector_valuetypes()) { in AMDGPUTargetLowering() local
292 for (MVT VT : ScalarIntVTs) { in AMDGPUTargetLowering() local
363 for (MVT VT : VectorIntTypes) { in AMDGPUTargetLowering() local
406 for (MVT VT : FloatVectorTypes) { in AMDGPUTargetLowering() local
768 EVT VT = EVT::getEVT(InitTy); in LowerConstantInitializer() local
776 EVT VT = EVT::getEVT(CFP->getType()); in LowerConstantInitializer() local
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMFastISel.cpp475 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) { in ARMMoveToFPReg()
485 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) { in ARMMoveToIntReg()
498 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) { in ARMMaterializeFP()
542 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) { in ARMMaterializeInt()
582 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) { in ARMMaterializeGV()
644 EVT VT = TLI.getValueType(C->getType(), true); in TargetMaterializeConstant() local
663 MVT VT; in TargetMaterializeAlloca() local
685 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal()
697 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { in isLoadTypeLegal()
831 void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) { in ARMSimplifyAddress()
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/external/swiftshader/third_party/LLVM/lib/VMCore/
DValueTypes.cpp29 EVT VT; in getExtendedIntegerVT() local
35 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT, in getExtendedVectorVT()
/external/mesa3d/src/gallium/drivers/radeon/
DR600ISelLowering.cpp277 EVT VT = Op.getValueType(); in LowerOperation() local
357 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT, in LowerImplicitParameter()
377 EVT VT = Op.getValueType(); in LowerROTL() local
390 EVT VT = Op.getValueType(); in LowerSELECT_CC() local
DAMDGPUISelLowering.cpp106 EVT VT = Op.getValueType(); in LowerINTRINSIC_WO_CHAIN() local
154 EVT VT = Op.getValueType(); in LowerIntrinsicIABS() local
167 EVT VT = Op.getValueType(); in LowerIntrinsicLRP() local
184 EVT VT = Op.getValueType(); in LowerUDIVREM() local
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h532 bool bitsGT(MVT VT) const { in bitsGT()
537 bool bitsGE(MVT VT) const { in bitsGE()
542 bool bitsLT(MVT VT) const { in bitsLT()
547 bool bitsLE(MVT VT) const { in bitsLE()
588 static MVT getVectorVT(MVT VT, unsigned NumElements) { in getVectorVT()
673 SimpleValueType VT; member
/external/llvm/lib/Target/X86/
DX86FastISel.cpp320 bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) { in isTypeLegal()
348 bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM, in X86FastEmitLoad()
501 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill, in X86FastEmitStore()
649 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val, in X86FastEmitStore()
1116 MVT VT; in X86SelectStore() local
1304 MVT VT; in X86SelectLoad() local
1328 static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) { in X86ChooseCmpOpcode()
1348 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) { in X86ChooseCmpImmediateOpcode()
1375 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1, EVT VT, in X86FastEmitCompare()
1411 MVT VT; in X86SelectCmp() local
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp212 for (MVT VT : MVT::vector_valuetypes()) { in AArch64TargetLowering() local
227 for (MVT VT : MVT::vector_valuetypes()) { in AArch64TargetLowering() local
419 for (MVT VT : MVT::fp_valuetypes()) { in AArch64TargetLowering() local
425 for (MVT VT : MVT::integer_valuetypes()) in AArch64TargetLowering() local
602 for (MVT VT : MVT::vector_valuetypes()) { in AArch64TargetLowering() local
634 void AArch64TargetLowering::addTypeForNEON(MVT VT, MVT PromotedBitwiseVT) { in addTypeForNEON()
717 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) { in addDRTypeForNEON()
722 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) { in addQRTypeForNEON()
759 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT(); in computeKnownBitsForTargetNode() local
779 MVT VT = Op.getOperand(1).getValueType().getSimpleVT(); in computeKnownBitsForTargetNode() local
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