1 /*
2 * Copyright (C) 2015 The Android Open Source Project
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in
12 * the documentation and/or other materials provided with the
13 * distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
18 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
19 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
25 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <errno.h>
30 #define __STDC_FORMAT_MACROS
31 #include <inttypes.h>
32 #include <stdio.h>
33 #include <stdlib.h>
34 #include <string.h>
35 #include <sys/mman.h>
36 #include <unistd.h>
37
38 #include <android/log.h>
39 #include <cutils/ashmem.h>
40
41 #include "codeflinger/ARMAssemblerInterface.h"
42 #include "codeflinger/MIPS64Assembler.h"
43
44 using namespace android;
45
46 #define TESTS_DATAOP_ENABLE 1
47 #define TESTS_DATATRANSFER_ENABLE 1
48 #define ASSEMBLY_SCRATCH_SIZE 4096
49
50 void *instrMem;
51 uint32_t instrMemSize = 128 * 1024;
52 char dataMem[8192];
53
54 typedef void (*asm_function_t)();
55 extern "C" void asm_mips_test_jacket(asm_function_t function,
56 int64_t regs[], int32_t flags[]);
57
58 #define MAX_32BIT (uint32_t)(((uint64_t)1 << 32) - 1)
59 #define MAX_64BIT ((uint64_t)0xFFFFFFFFFFFFFFFF)
60 const uint32_t NA = 0;
61 const uint32_t NUM_REGS = 32;
62 const uint32_t NUM_FLAGS = 16;
63
64 enum instr_t
65 {
66 INSTR_ADD,
67 INSTR_SUB,
68 INSTR_AND,
69 INSTR_ORR,
70 INSTR_RSB,
71 INSTR_BIC,
72 INSTR_CMP,
73 INSTR_MOV,
74 INSTR_MVN,
75 INSTR_MUL,
76 INSTR_MLA,
77 INSTR_SMULBB,
78 INSTR_SMULBT,
79 INSTR_SMULTB,
80 INSTR_SMULTT,
81 INSTR_SMULWB,
82 INSTR_SMULWT,
83 INSTR_SMLABB,
84 INSTR_UXTB16,
85 INSTR_UBFX,
86 INSTR_ADDR_ADD,
87 INSTR_ADDR_SUB,
88 INSTR_LDR,
89 INSTR_LDRB,
90 INSTR_LDRH,
91 INSTR_ADDR_LDR,
92 INSTR_LDM,
93 INSTR_STR,
94 INSTR_STRB,
95 INSTR_STRH,
96 INSTR_ADDR_STR,
97 INSTR_STM
98 };
99
100 enum shift_t
101 {
102 SHIFT_LSL,
103 SHIFT_LSR,
104 SHIFT_ASR,
105 SHIFT_ROR,
106 SHIFT_NONE
107 };
108
109 enum offset_t
110 {
111 REG_SCALE_OFFSET,
112 REG_OFFSET,
113 IMM8_OFFSET,
114 IMM12_OFFSET,
115 NO_OFFSET
116 };
117
118 enum cond_t
119 {
120 EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV,
121 HS = CS,
122 LO = CC
123 };
124
125 const char * cc_code[] =
126 {
127 "EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC",
128 "HI", "LS","GE","LT", "GT", "LE", "AL", "NV"
129 };
130
131 struct condTest_t
132 {
133 int mode;
134 int32_t Rcond1;
135 int32_t Rcond2;
136 uint64_t Rcond1Value;
137 uint64_t Rcond2Value;
138 };
139
140
141 struct dataOpTest_t
142 {
143 uint32_t id;
144 instr_t op;
145 condTest_t preCond;
146 cond_t cond;
147 bool setFlags;
148 uint64_t RnValue;
149 uint64_t RsValue;
150 bool immediate;
151 uint32_t immValue;
152 uint64_t RmValue;
153 uint32_t shiftMode;
154 uint32_t shiftAmount;
155 uint64_t RdValue;
156 bool checkRd;
157 uint64_t postRdValue;
158 };
159
160 struct dataTransferTest_t
161 {
162 uint32_t id;
163 instr_t op;
164 uint32_t preFlag;
165 cond_t cond;
166 bool setMem;
167 uint64_t memOffset;
168 uint64_t memValue;
169 uint64_t RnValue;
170 offset_t offsetType;
171 uint64_t RmValue;
172 uint32_t immValue;
173 bool writeBack;
174 bool preIndex;
175 bool postIndex;
176 uint64_t RdValue;
177 uint64_t postRdValue;
178 uint64_t postRnValue;
179 bool checkMem;
180 uint64_t postMemOffset;
181 uint32_t postMemLength;
182 uint64_t postMemValue;
183 };
184
185
186 dataOpTest_t dataOpTests [] =
187 {
188 {0xA000,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,1,MAX_32BIT,NA,NA,NA,NA,1,0},
189 {0xA001,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,1,MAX_32BIT-1,NA,NA,NA,NA,1,MAX_64BIT},
190 {0xA002,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,NA,MAX_32BIT,NA,NA,NA,1,0},
191 {0xA003,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,NA,MAX_32BIT-1,NA,NA,NA,1,MAX_64BIT},
192 {0xA004,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSL, 0,NA,1,0},
193 {0xA005,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSL,31,NA,1,0xFFFFFFFF80000001},
194 {0xA006,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,0,3,SHIFT_LSR,1,NA,1,2},
195 {0xA007,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSR,31,NA,1,2},
196 {0xA008,INSTR_ADD,{0,0,0,0,0},AL,0,0,NA,0,0,3,SHIFT_ASR,1,NA,1,1},
197 {0xA009,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_64BIT,SHIFT_ASR,31,NA,1,0},
198 {0xA010,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,1,MAX_32BIT,0,0,0,NA,1,1},
199 {0xA011,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,1,MAX_32BIT-1,0,0,0,NA,1,0},
200 {0xA012,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,0,0,NA,1,1},
201 {0xA013,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT-1,0,0,NA,1,0},
202 {0xA014,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSL,0,NA,1,1},
203 {0xA015,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSL,31,NA,1,0},
204 {0xA016,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,0,0,3,SHIFT_LSR,1,NA,1,1},
205 {0xA017,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSR,31,NA,1,1},
206 {0xA018,INSTR_AND,{0,0,0,0,0},AL,0,0,NA,0,0,3,SHIFT_ASR,1,NA,1,0},
207 {0xA019,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_ASR,31,NA,1,1},
208 {0xA020,INSTR_ORR,{0,0,0,0,0},AL,0,3,NA,1,MAX_32BIT,0,0,0,NA,1,MAX_64BIT},
209 {0xA021,INSTR_ORR,{0,0,0,0,0},AL,0,2,NA,1,MAX_32BIT-1,0,0,0,NA,1,MAX_64BIT-1},
210 {0xA022,INSTR_ORR,{0,0,0,0,0},AL,0,3,NA,0,0,MAX_32BIT,0,0,NA,1,MAX_64BIT},
211 {0xA023,INSTR_ORR,{0,0,0,0,0},AL,0,2,NA,0,0,MAX_32BIT-1,0,0,NA,1,MAX_64BIT-1},
212 {0xA024,INSTR_ORR,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSL,0,NA,1,MAX_64BIT},
213 {0xA025,INSTR_ORR,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSL,31,NA,1,0xFFFFFFFF80000001},
214 {0xA026,INSTR_ORR,{0,0,0,0,0},AL,0,1,NA,0,0,3,SHIFT_LSR,1,NA,1,1},
215 {0xA027,INSTR_ORR,{0,0,0,0,0},AL,0,0,NA,0,0,MAX_32BIT,SHIFT_LSR,31,NA,1,1},
216 {0xA028,INSTR_ORR,{0,0,0,0,0},AL,0,0,NA,0,0,3,SHIFT_ASR,1,NA,1,1},
217 {0xA029,INSTR_ORR,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_64BIT,SHIFT_ASR,31,NA,1,MAX_64BIT},
218 {0xA030,INSTR_CMP,{0,0,0,0,0},AL,1,0x10000,NA,1,0x10000,0,0,0,NA,0,0},
219 {0xA031,INSTR_MUL,{0,0,0,0,0},AL,0,0,0x10000,0,0,0x10000,0,0,NA,1,0},
220 {0xA032,INSTR_MUL,{0,0,0,0,0},AL,0,0,0x1000,0,0,0x10000,0,0,NA,1,0x10000000},
221 {0xA033,INSTR_MUL,{0,0,0,0,0},AL,0,0,MAX_32BIT,0,0,1,0,0,NA,1,MAX_64BIT},
222 {0xA034,INSTR_MLA,{0,0,0,0,0},AL,0,0x10000,0x10000,0,0,0x10000,0,0,NA,1,0x10000},
223 {0xA035,INSTR_MLA,{0,0,0,0,0},AL,0,0x10000,0x1000,0,0,0x10000,0,0,NA,1,0x10010000},
224 {0xA036,INSTR_SUB,{1,R_v1,R_a6,2,4},MI,0,2,NA,0,NA,1,NA,NA,2,1,1},
225 {0xA037,INSTR_SUB,{2,R_v1,R_a6,2,0},MI,0,2,NA,0,NA,1,NA,NA,2,1,2},
226 {0xA038,INSTR_SUB,{1,R_v1,R_a6,4,2},GE,0,2,NA,1,1,NA,NA,NA,2,1,1},
227 {0xA039,INSTR_SUB,{1,R_a5,R_a6,2,7},GE,0,2,NA,1,1,NA,NA,NA,2,1,2},
228 {0xA040,INSTR_SUB,{1,R_a5,R_a6,1,1},HS,0,2,NA,1,1,NA,NA,NA,2,1,1},
229 {0xA041,INSTR_SUB,{1,R_a5,R_a6,0,1},HS,0,2,NA,1,1,NA,NA,NA,2,1,2},
230 {0xA042,INSTR_SUB,{0,0,0,0,0},AL,0,1,NA,1,1<< 16,0,0,0,NA,1,UINT64_C(1) -(1<<16)},
231 {0xA043,INSTR_SUB,{0,0,0,0,0},AL,0,MAX_32BIT,NA,1,1,0,0,0,NA,1,MAX_64BIT-1},
232 {0xA044,INSTR_SUB,{0,0,0,0,0},AL,0,1,NA,1,1,0,0,0,NA,1,0},
233 {0xA045,INSTR_SUB,{0,0,0,0,0},AL,0,1,NA,0,NA,1<<16,0,0,NA,1,UINT64_C(1) -(1<<16)},
234 {0xA046,INSTR_SUB,{0,0,0,0,0},AL,0,MAX_32BIT,NA,0,NA,1,0,0,NA,1,MAX_64BIT-1},
235 {0xA047,INSTR_SUB,{0,0,0,0,0},AL,0,1,NA,0,NA,1,0,0,NA,1,0},
236 {0xA048,INSTR_SUB,{0,0,0,0,0},AL,0,1,NA,0,NA,1,SHIFT_LSL,16,NA,1,UINT64_C(1) -(1<<16)},
237 {0xA049,INSTR_SUB,{0,0,0,0,0},AL,0,0x80000001,NA,0,NA,MAX_32BIT,SHIFT_LSL,31,NA,1,1},
238 {0xA050,INSTR_SUB,{0,0,0,0,0},AL,0,1,NA,0,NA,3,SHIFT_LSR,1,NA,1,0},
239 {0xA051,INSTR_SUB,{0,0,0,0,0},AL,0,1,NA,0,NA,MAX_32BIT,SHIFT_LSR,31,NA,1,0},
240 {0xA052,INSTR_RSB,{1,R_a5,R_a6,4,1},GE,0,2,NA,1,0,NA,NA,NA,2,1,UINT64_C(-2)},
241 {0xA053,INSTR_RSB,{1,R_a5,R_a6,UINT64_C(-1),1},GE,0,2,NA,1,0,NA,NA,NA,2,1,2},
242 {0xA054,INSTR_RSB,{0,0,0,0,0},AL,0,1,NA,1,1<<16,NA,NA,NA,NA,1,(1<<16)-1},
243 {0xA055,INSTR_RSB,{0,0,0,0,0},AL,0,MAX_32BIT,NA,1,1,NA,NA,NA,NA,1,UINT64_C(1)-MAX_64BIT},
244 {0xA056,INSTR_RSB,{0,0,0,0,0},AL,0,1,NA,1,1,NA,NA,NA,NA,1,0},
245 {0xA057,INSTR_RSB,{0,0,0,0,0},AL,0,1,NA,0,NA,1<<16,0,0,NA,1,(1<<16)-1},
246 {0xA058,INSTR_RSB,{0,0,0,0,0},AL,0,MAX_32BIT,NA,0,NA,1,0,0,NA,1,UINT64_C(1)-MAX_64BIT},
247 {0xA059,INSTR_RSB,{0,0,0,0,0},AL,0,1,NA,0,NA,1,0,0,NA,1,0},
248 {0xA060,INSTR_RSB,{0,0,0,0,0},AL,0,1,NA,0,NA,1,SHIFT_LSL,16,NA,1,(1<<16)-1},
249 {0xA061,INSTR_RSB,{0,0,0,0,0},AL,0,0x80000001,NA,0,NA,MAX_32BIT ,SHIFT_LSL,31,NA,1,UINT64_C(-1)},
250 {0xA062,INSTR_RSB,{0,0,0,0,0},AL,0,1,NA,0,NA,3,SHIFT_LSR,1,NA,1,0},
251 {0xA063,INSTR_RSB,{0,0,0,0,0},AL,0,1,NA,0,NA,MAX_32BIT,SHIFT_LSR,31,NA,1,0},
252 {0xA064,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,1,0x80000001,NA,NA,NA,NA,1,0xFFFFFFFF80000001},
253 {0xA065,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,0x80000001,0,0,NA,1,0xFFFFFFFF80000001},
254 {0xA066,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,1,NA,1,MAX_64BIT-1},
255 {0xA067,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,31,NA,1,0xFFFFFFFF80000000},
256 {0xA068,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,3,SHIFT_LSR,1,NA,1,1},
257 {0xA069,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSR,31,NA,1,1},
258 {0xA070,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,3,SHIFT_ASR,1,NA,1,1},
259 {0xA071,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,MAX_64BIT ,SHIFT_ASR,31,NA,1,MAX_64BIT},
260 {0xA072,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,3,SHIFT_ROR,1,NA,1,0xFFFFFFFF80000001},
261 {0xA073,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,0x80000001,SHIFT_ROR,31,NA,1,3},
262 {0xA074,INSTR_MOV,{0,0,0,0,0},AL,1,NA,NA,0,0,MAX_64BIT -1,SHIFT_ASR,1,NA,1,MAX_64BIT},
263 {0xA075,INSTR_MOV,{0,0,0,0,0},AL,1,NA,NA,0,0,3,SHIFT_ASR,1,NA,1,1},
264 {0xA076,INSTR_MOV,{2,R_a5,R_a6,6,8},MI,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,2},
265 {0xA077,INSTR_MOV,{2,R_a5,R_a6,UINT64_C(-4),UINT64_C(-8)},MI,0,NA,NA,0,0,0x80000001,0,0,2,1,0xFFFFFFFF80000001},
266 {0xA078,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),UINT64_C(-1)},LT,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,2},
267 {0xA079,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),1},LT,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,0xFFFFFFFF80000001},
268 {0xA080,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),UINT64_C(-5)},GE,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,1,2,1,MAX_64BIT-1},
269 {0xA081,INSTR_MOV,{1,R_a5,R_a6,5,5},GE,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,31,2,1,0xFFFFFFFF80000000},
270 {0xA082,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),1},GE,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,31,2,1,2},
271 {0xA083,INSTR_MOV,{1,R_a5,R_a6,4,1},LE,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,1,2,1,2},
272 {0xA084,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),UINT64_C(-1)},LE,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,0xFFFFFFFF80000001},
273 {0xA085,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),1},LE,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,31,2,1,0xFFFFFFFF80000000},
274 {0xA086,INSTR_MOV,{1,R_a5,R_a6,1,1},GT,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,2},
275 {0xA087,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),UINT64_C(-3)},GT,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,0xFFFFFFFF80000001},
276 {0xA088,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),0},GT,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,2},
277 {0xA089,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),UINT64_C(-1)},GT,0,NA,NA,0,0,0x80000001,0,0,2,1,2},
278 {0xA090,INSTR_MOV,{1,R_a5,R_a6,6,1},GT,0,NA,NA,0,0,0x80000001,0,0,2,1,0xFFFFFFFF80000001},
279 {0xA091,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),1},GT,0,NA,NA,0,0,0x80000001,0,0,2,1,2},
280 {0xA092,INSTR_MOV,{1,R_a5,R_a6,1,1},GT,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,1,2,1,2},
281 {0xA093,INSTR_MOV,{1,R_a5,R_a6,4,1},GT,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,1,2,1,MAX_64BIT-1},
282 {0xA094,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),1},GT,0,NA,NA,0,0,MAX_32BIT ,SHIFT_LSL,1,2,1,2},
283 {0xA095,INSTR_MOV,{1,R_a5,R_a6,1,UINT64_C(-1)},HS,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,2},
284 {0xA096,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),1},HS,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,0xFFFFFFFF80000001},
285 {0xA097,INSTR_MVN,{1,R_a5,R_a6,1,4},HS,0,NA,NA,1,MAX_32BIT-1,NA,NA,NA,2,1,2},
286 {0xA098,INSTR_MVN,{1,R_a5,R_a6,UINT64_C(-1),1},HS,0,NA,NA,1,MAX_32BIT-1,NA,NA,NA,2,1,1},
287 {0xA099,INSTR_MVN,{0,0,0,0,0},AL,0,NA,NA,1,0,NA,NA,NA,2,1,MAX_64BIT},
288 {0xA100,INSTR_MVN,{0,0,0,0,0},AL,0,NA,NA,0,NA,MAX_32BIT-1,NA,0,2,1,1},
289 {0xA101,INSTR_MVN,{0,0,0,0,0},AL,0,NA,NA,0,NA,0x80000001,NA,0,2,1,0x7FFFFFFE},
290 {0xA102,INSTR_BIC,{0,0,0,0,0},AL,0,1,NA,1,MAX_32BIT,NA,NA,NA,NA,1,0},
291 {0xA103,INSTR_BIC,{0,0,0,0,0},AL,0,1,NA,1,MAX_32BIT-1,NA,NA,NA,NA,1,1},
292 {0xA104,INSTR_BIC,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,0,0,NA,1,0},
293 {0xA105,INSTR_BIC,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT-1,0,0,NA,1,1},
294 {0xA106,INSTR_BIC,{0,0,0,0,0},AL,0,0xF0,NA,0,0,3,SHIFT_ASR,1,NA,1,0xF0},
295 {0xA107,INSTR_BIC,{0,0,0,0,0},AL,0,0xF0,NA,0,0,MAX_64BIT,SHIFT_ASR,31,NA,1,0},
296 {0xA108,INSTR_SMULBB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCDFFFF,0,NA,0xFFFFFFFFABCD0001,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF},
297 {0xA109,INSTR_SMULBB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCD0001,0,NA,0xFFFFFFFFABCD0FFF,NA,NA,NA,1,0x00000FFF},
298 {0xA110,INSTR_SMULBB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCD0001,0,NA,0xFFFFFFFFABCDFFFF,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF},
299 {0xA111,INSTR_SMULBB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCDFFFF,0,NA,0xFFFFFFFFABCDFFFF,NA,NA,NA,1,1},
300 {0xA112,INSTR_SMULBT,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFFFFFABCD,0,NA,0xFFFFFFFFABCD0001,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF},
301 {0xA113,INSTR_SMULBT,{0,0,0,0,0},AL,0,NA,0x000000000001ABCD,0,NA,0xFFFFFFFFABCD0FFF,NA,NA,NA,1,0x00000FFF},
302 {0xA114,INSTR_SMULBT,{0,0,0,0,0},AL,0,NA,0x000000000001ABCD,0,NA,0xFFFFFFFFABCDFFFF,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF},
303 {0xA115,INSTR_SMULBT,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFFFFFABCD,0,NA,0xFFFFFFFFABCDFFFF,NA,NA,NA,1,1},
304 {0xA116,INSTR_SMULTB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCDFFFF,0,NA,0x000000000001ABCD,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF},
305 {0xA117,INSTR_SMULTB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCD0001,0,NA,0x000000000FFFABCD,NA,NA,NA,1,0x00000FFF},
306 {0xA118,INSTR_SMULTB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCD0001,0,NA,0xFFFFFFFFFFFFABCD,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF},
307 {0xA119,INSTR_SMULTB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCDFFFF,0,NA,0xFFFFFFFFFFFFABCD,NA,NA,NA,1,1},
308 {0xA120,INSTR_SMULTT,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFFFFFABCD,0,NA,0x000000000001ABCD,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF},
309 {0xA121,INSTR_SMULTT,{0,0,0,0,0},AL,0,NA,0x000000000001ABCD,0,NA,0x000000000FFFABCD,NA,NA,NA,1,0x00000FFF},
310 {0xA122,INSTR_SMULTT,{0,0,0,0,0},AL,0,NA,0x000000000001ABCD,0,NA,0xFFFFFFFFFFFFABCD,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF},
311 {0xA123,INSTR_SMULTT,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFFFFFABCD,0,NA,0xFFFFFFFFFFFFABCD,NA,NA,NA,1,1},
312 {0xA124,INSTR_SMULWB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCDFFFF,0,NA,0x000000000001ABCD,NA,NA,NA,1,0xFFFFFFFFFFFFFFFE},
313 {0xA125,INSTR_SMULWB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCD0001,0,NA,0x000000000FFFABCD,NA,NA,NA,1,0x00000FFF},
314 {0xA126,INSTR_SMULWB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCD0001,0,NA,0xFFFFFFFFFFFFABCD,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF},
315 {0xA127,INSTR_SMULWB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCDFFFF,0,NA,0xFFFFFFFFFFFFABCD,NA,NA,NA,1,0},
316 {0xA128,INSTR_SMULWT,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFFFFFABCD,0,NA,0x000000000001ABCD,NA,NA,NA,1,0xFFFFFFFFFFFFFFFE},
317 {0xA129,INSTR_SMULWT,{0,0,0,0,0},AL,0,NA,0x000000000001ABCD,0,NA,0x000000000FFFABCD,NA,NA,NA,1,0x00000FFF},
318 {0xA130,INSTR_SMULWT,{0,0,0,0,0},AL,0,NA,0x000000000001ABCD,0,NA,0xFFFFFFFFFFFFABCD,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF},
319 {0xA131,INSTR_SMULWT,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFFFFFABCD,0,NA,0xFFFFFFFFFFFFABCD,NA,NA,NA,1,0},
320 {0xA132,INSTR_SMLABB,{0,0,0,0,0},AL,0,1,0xFFFFFFFFABCDFFFF,0,NA,0xFFFFFFFFABCD0001,NA,NA,NA,1,0},
321 {0xA133,INSTR_SMLABB,{0,0,0,0,0},AL,0,1,0xFFFFFFFFABCD0001,0,NA,0xFFFFFFFFABCD0FFF,NA,NA,NA,1,0x00001000},
322 {0xA134,INSTR_SMLABB,{0,0,0,0,0},AL,0,0xFFFFFFFFFFFFFFFF,0xFFFFFFFFABCD0001,0,NA,0xABCDFFFF,NA,NA,NA,1,0xFFFFFFFFFFFFFFFE},
323 {0xA135,INSTR_SMLABB,{0,0,0,0,0},AL,0,0xFFFFFFFFFFFFFFFF,0xFFFFFFFFABCDFFFF,0,NA,0xABCDFFFF,NA,NA,NA,1,0},
324 {0xA136,INSTR_UXTB16,{0,0,0,0,0},AL,0,NA,NA,0,NA,0xABCDEF01,SHIFT_ROR,0,NA,1,0x00CD0001},
325 {0xA137,INSTR_UXTB16,{0,0,0,0,0},AL,0,NA,NA,0,NA,0xABCDEF01,SHIFT_ROR,1,NA,1,0x00AB00EF},
326 {0xA138,INSTR_UXTB16,{0,0,0,0,0},AL,0,NA,NA,0,NA,0xABCDEF01,SHIFT_ROR,2,NA,1,0x000100CD},
327 {0xA139,INSTR_UXTB16,{0,0,0,0,0},AL,0,NA,NA,0,NA,0xABCDEF01,SHIFT_ROR,3,NA,1,0x00EF00AB},
328 {0xA140,INSTR_ADDR_ADD,{0,0,0,0,0},AL,0,0xCFFFFFFFF,NA,0,NA,0x1,SHIFT_LSL,1,NA,1,0xD00000001},
329 {0xA141,INSTR_ADDR_ADD,{0,0,0,0,0},AL,0,0x01,NA,0,NA,0x1,SHIFT_LSL,2,NA,1,0x5},
330 {0xA142,INSTR_ADDR_ADD,{0,0,0,0,0},AL,0,0xCFFFFFFFF,NA,0,NA,0x1,NA,0,NA,1,0xD00000000},
331 {0xA143,INSTR_ADDR_SUB,{0,0,0,0,0},AL,0,0xD00000001,NA,0,NA,0x010000,SHIFT_LSR,15,NA,1,0xCFFFFFFFF},
332 {0xA144,INSTR_ADDR_SUB,{0,0,0,0,0},AL,0,0xCFFFFFFFF,NA,0,NA,0x020000,SHIFT_LSR,15,NA,1,0xCFFFFFFFB},
333 {0xA145,INSTR_ADDR_SUB,{0,0,0,0,0},AL,0,3,NA,0,NA,0x010000,SHIFT_LSR,15,NA,1,1},
334 };
335
336 dataTransferTest_t dataTransferTests [] =
337 {
338 {0xB000,INSTR_LDR,AL,AL,1,24,0xABCDEF0123456789,0,REG_SCALE_OFFSET,24,NA,NA,NA,NA,NA,0x23456789,0,0,NA,NA,NA},
339 {0xB001,INSTR_LDR,AL,AL,1,0,0xABCDEF0123456789,0,IMM12_OFFSET,NA,4,1,0,1,NA,0x23456789,4,0,NA,NA,NA},
340 {0xB002,INSTR_LDR,AL,AL,1,0,0xABCDEF0123456789,0,NO_OFFSET,NA,NA,0,0,0,NA,0x23456789,0,0,NA,NA,NA},
341 {0xB003,INSTR_LDRB,AL,AL,1,4064,0xABCDEF0123456789,0,REG_SCALE_OFFSET,4064,NA,NA,NA,NA,NA,0x89,0,0,NA,NA,NA},
342 {0xB004,INSTR_LDRB,AL,AL,1,4064,0xABCDEF0123456789,4065,IMM12_OFFSET,NA,0,0,1,0,NA,0x67,4065,0,NA,NA,NA},
343 {0xB005,INSTR_LDRB,AL,AL,1,4064,0xABCDEF0123456789,4065,IMM12_OFFSET,NA,1,0,1,0,NA,0x45,4065,0,NA,NA,NA},
344 {0xB006,INSTR_LDRB,AL,AL,1,4064,0xABCDEF0123456789,4065,IMM12_OFFSET,NA,2,0,1,0,NA,0x23,4065,0,NA,NA,NA},
345 {0xB007,INSTR_LDRB,AL,AL,1,4064,0xABCDEF0123456789,4065,IMM12_OFFSET,NA,1,1,0,1,NA,0x67,4066,0,NA,NA,NA},
346 {0xB008,INSTR_LDRB,AL,AL,1,4064,0xABCDEF0123456789,0,NO_OFFSET,NA,NA,0,0,0,NA,0x89,0,0,NA,NA,NA},
347 {0xB009,INSTR_LDRH,AL,AL,1,0,0xABCDEF0123456789,0,IMM8_OFFSET,NA,2,1,0,1,NA,0x6789,2,0,NA,NA,NA},
348 {0xB010,INSTR_LDRH,AL,AL,1,4064,0xABCDEF0123456789,0,REG_OFFSET,4064,0,0,1,0,NA,0x6789,0,0,NA,NA,NA},
349 {0xB011,INSTR_LDRH,AL,AL,1,4064,0xABCDEF0123456789,0,REG_OFFSET,4066,0,0,1,0,NA,0x2345,0,0,NA,NA,NA},
350 {0xB012,INSTR_LDRH,AL,AL,1,0,0xABCDEF0123456789,0,NO_OFFSET,NA,0,0,0,0,NA,0x6789,0,0,NA,NA,NA},
351 {0xB013,INSTR_LDRH,AL,AL,1,0,0xABCDEF0123456789,2,NO_OFFSET,NA,0,0,0,0,NA,0x2345,2,0,NA,NA,NA},
352 {0xB014,INSTR_STR,AL,AL,1,2,0xDEADBEEFDEADBEEF,4,IMM12_OFFSET,NA,4,1,0,1,0xABCDEF0123456789,0xABCDEF0123456789,8,1,2,8,0xDEAD23456789BEEF},
353 {0xB015,INSTR_STR,AL,AL,1,2,0xDEADBEEFDEADBEEF,4,NO_OFFSET,NA,NA,0,0,0,0xABCDEF0123456789,0xABCDEF0123456789,4,1,2,8,0xDEAD23456789BEEF},
354 {0xB016,INSTR_STRB,AL,AL,1,0,0xDEADBEEFDEADBEEF,1,IMM12_OFFSET,NA,0,0,1,0,0xABCDEF0123456789,0xABCDEF0123456789,1,1,0,8,0xDEADBEEFDEAD89EF},
355 {0xB017,INSTR_STRB,AL,AL,1,0,0xDEADBEEFDEADBEEF,1,IMM12_OFFSET,NA,1,0,1,0,0xABCDEF0123456789,0xABCDEF0123456789,1,1,0,8,0xDEADBEEFDE89BEEF},
356 {0xB018,INSTR_STRB,AL,AL,1,0,0xDEADBEEFDEADBEEF,1,IMM12_OFFSET,NA,2,0,1,0,0xABCDEF0123456789,0xABCDEF0123456789,1,1,0,8,0xDEADBEEF89ADBEEF},
357 {0xB019,INSTR_STRB,AL,AL,1,0,0xDEADBEEFDEADBEEF,1,IMM12_OFFSET,NA,4,1,0,1,0xABCDEF0123456789,0xABCDEF0123456789,5,1,0,8,0xDEADBEEFDEAD89EF},
358 {0xB020,INSTR_STRB,AL,AL,1,0,0xDEADBEEFDEADBEEF,1,NO_OFFSET,NA,NA,0,0,0,0xABCDEF0123456789,0xABCDEF0123456789,1,1,0,8,0xDEADBEEFDEAD89EF},
359 {0xB021,INSTR_STRH,AL,AL,1,4066,0xDEADBEEFDEADBEEF,4070,IMM8_OFFSET,NA,2,1,0,1,0xABCDEF0123456789,0xABCDEF0123456789,4072,1,4066,8,0xDEAD6789DEADBEEF},
360 {0xB022,INSTR_STRH,AL,AL,1,4066,0xDEADBEEFDEADBEEF,4070,NO_OFFSET,NA,NA,0,0,0,0xABCDEF0123456789,0xABCDEF0123456789,4070,1,4066,8,0xDEAD6789DEADBEEF},
361 };
362
363
flushcache()364 void flushcache()
365 {
366 const long base = long(instrMem);
367 const long curr = base + long(instrMemSize);
368 __builtin___clear_cache((char*)base, (char*)curr);
369 }
370
dataOpTest(dataOpTest_t test,ArmToMips64Assembler * a64asm,uint32_t Rd=R_v1,uint32_t Rn=R_t0,uint32_t Rm=R_t1,uint32_t Rs=R_t2)371 void dataOpTest(dataOpTest_t test, ArmToMips64Assembler *a64asm, uint32_t Rd = R_v1,
372 uint32_t Rn = R_t0, uint32_t Rm = R_t1, uint32_t Rs = R_t2)
373 {
374 int64_t regs[NUM_REGS] = {0};
375 int32_t flags[NUM_FLAGS] = {0};
376 int64_t savedRegs[NUM_REGS] = {0};
377 uint32_t i;
378 uint32_t op2;
379
380 for(i = 0; i < NUM_REGS; ++i)
381 {
382 regs[i] = i;
383 }
384
385 regs[Rd] = test.RdValue;
386 regs[Rn] = test.RnValue;
387 regs[Rs] = test.RsValue;
388 a64asm->reset();
389 if (test.preCond.mode) {
390 a64asm->set_condition(test.preCond.mode, test.preCond.Rcond1, test.preCond.Rcond2);
391 regs[test.preCond.Rcond1] = test.preCond.Rcond1Value;
392 regs[test.preCond.Rcond2] = test.preCond.Rcond2Value;
393 }
394 a64asm->prolog();
395 if(test.immediate == true)
396 {
397 op2 = a64asm->imm(test.immValue);
398 }
399 else if(test.immediate == false && test.shiftAmount == 0)
400 {
401 op2 = Rm;
402 regs[Rm] = (int64_t)((int32_t)(test.RmValue));
403 }
404 else
405 {
406 op2 = a64asm->reg_imm(Rm, test.shiftMode, test.shiftAmount);
407 regs[Rm] = (int64_t)((int32_t)(test.RmValue));
408 }
409 switch(test.op)
410 {
411 case INSTR_ADD: a64asm->ADD(test.cond, test.setFlags, Rd,Rn,op2); break;
412 case INSTR_SUB: a64asm->SUB(test.cond, test.setFlags, Rd,Rn,op2); break;
413 case INSTR_RSB: a64asm->RSB(test.cond, test.setFlags, Rd,Rn,op2); break;
414 case INSTR_AND: a64asm->AND(test.cond, test.setFlags, Rd,Rn,op2); break;
415 case INSTR_ORR: a64asm->ORR(test.cond, test.setFlags, Rd,Rn,op2); break;
416 case INSTR_BIC: a64asm->BIC(test.cond, test.setFlags, Rd,Rn,op2); break;
417 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break;
418 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break;
419 case INSTR_CMP: a64asm->CMP(test.cond, Rn,op2); break;
420 case INSTR_MOV: a64asm->MOV(test.cond, test.setFlags,Rd,op2); break;
421 case INSTR_MVN: a64asm->MVN(test.cond, test.setFlags,Rd,op2); break;
422 case INSTR_SMULBB:a64asm->SMULBB(test.cond, Rd,Rm,Rs); break;
423 case INSTR_SMULBT:a64asm->SMULBT(test.cond, Rd,Rm,Rs); break;
424 case INSTR_SMULTB:a64asm->SMULTB(test.cond, Rd,Rm,Rs); break;
425 case INSTR_SMULTT:a64asm->SMULTT(test.cond, Rd,Rm,Rs); break;
426 case INSTR_SMULWB:a64asm->SMULWB(test.cond, Rd,Rm,Rs); break;
427 case INSTR_SMULWT:a64asm->SMULWT(test.cond, Rd,Rm,Rs); break;
428 case INSTR_SMLABB:a64asm->SMLABB(test.cond, Rd,Rm,Rs,Rn); break;
429 case INSTR_UXTB16:a64asm->UXTB16(test.cond, Rd,Rm,test.shiftAmount); break;
430 case INSTR_ADDR_ADD: a64asm->ADDR_ADD(test.cond, test.setFlags, Rd,Rn,op2); break;
431 case INSTR_ADDR_SUB: a64asm->ADDR_SUB(test.cond, test.setFlags, Rd,Rn,op2); break;
432 default: printf("Error"); return;
433 }
434 a64asm->epilog(0);
435 a64asm->fix_branches();
436 flushcache();
437
438 asm_function_t asm_function = (asm_function_t)(instrMem);
439
440 for(i = 0; i < NUM_REGS; ++i)
441 savedRegs[i] = regs[i];
442
443 asm_mips_test_jacket(asm_function, regs, flags);
444
445 /* Check if all regs except Rd is same */
446 for(i = 0; i < NUM_REGS; ++i)
447 {
448 if((i == Rd) || i == 2) continue;
449 if(regs[i] != savedRegs[i])
450 {
451 printf("Test %x failed Reg(%d) tampered Expected(0x%" PRIx64 "),"
452 "Actual(0x%" PRIx64 ") t\n", test.id, i, savedRegs[i],
453 regs[i]);
454 exit(0);
455 return;
456 }
457 }
458
459 if(test.checkRd == 1 && regs[Rd] != test.postRdValue)
460 {
461 printf("Test %x failed, Expected(%" PRIx64 "), Actual(%" PRIx64 ")\n",
462 test.id, test.postRdValue, regs[Rd]);
463 exit(0);
464 }
465 else
466 {
467 printf("Test %x passed\n", test.id);
468 }
469 }
470
471
dataTransferTest(dataTransferTest_t test,ARMAssemblerInterface * a64asm,uint32_t Rd=R_v1,uint32_t Rn=R_t0,uint32_t Rm=R_t1)472 void dataTransferTest(dataTransferTest_t test, ARMAssemblerInterface *a64asm,
473 uint32_t Rd = R_v1, uint32_t Rn = R_t0,uint32_t Rm = R_t1)
474 {
475 int64_t regs[NUM_REGS] = {0};
476 int64_t savedRegs[NUM_REGS] = {0};
477 int32_t flags[NUM_FLAGS] = {0};
478 uint32_t i;
479 for(i = 0; i < NUM_REGS; ++i)
480 {
481 regs[i] = i;
482 }
483
484 uint32_t op2;
485
486 regs[Rd] = test.RdValue;
487 regs[Rn] = (uint64_t)(&dataMem[test.RnValue]);
488 regs[Rm] = test.RmValue;
489 flags[test.preFlag] = 1;
490
491 if(test.setMem == true)
492 {
493 unsigned char *mem = (unsigned char *)&dataMem[test.memOffset];
494 uint64_t value = test.memValue;
495 for(int j = 0; j < 8; ++j)
496 {
497 mem[j] = value & 0x00FF;
498 value >>= 8;
499 }
500 }
501 a64asm->reset();
502 a64asm->prolog();
503 if(test.offsetType == REG_SCALE_OFFSET)
504 {
505 op2 = a64asm->reg_scale_pre(Rm);
506 }
507 else if(test.offsetType == REG_OFFSET)
508 {
509 op2 = a64asm->reg_pre(Rm);
510 }
511 else if(test.offsetType == IMM12_OFFSET && test.preIndex == true)
512 {
513 op2 = a64asm->immed12_pre(test.immValue, test.writeBack);
514 }
515 else if(test.offsetType == IMM12_OFFSET && test.postIndex == true)
516 {
517 op2 = a64asm->immed12_post(test.immValue);
518 }
519 else if(test.offsetType == IMM8_OFFSET && test.preIndex == true)
520 {
521 op2 = a64asm->immed8_pre(test.immValue, test.writeBack);
522 }
523 else if(test.offsetType == IMM8_OFFSET && test.postIndex == true)
524 {
525 op2 = a64asm->immed8_post(test.immValue);
526 }
527 else if(test.offsetType == NO_OFFSET)
528 {
529 op2 = a64asm->__immed12_pre(0);
530 }
531 else
532 {
533 printf("Error - Unknown offset\n"); return;
534 }
535
536 switch(test.op)
537 {
538 case INSTR_LDR: a64asm->LDR(test.cond, Rd,Rn,op2); break;
539 case INSTR_LDRB: a64asm->LDRB(test.cond, Rd,Rn,op2); break;
540 case INSTR_LDRH: a64asm->LDRH(test.cond, Rd,Rn,op2); break;
541 case INSTR_ADDR_LDR: a64asm->ADDR_LDR(test.cond, Rd,Rn,op2); break;
542 case INSTR_STR: a64asm->STR(test.cond, Rd,Rn,op2); break;
543 case INSTR_STRB: a64asm->STRB(test.cond, Rd,Rn,op2); break;
544 case INSTR_STRH: a64asm->STRH(test.cond, Rd,Rn,op2); break;
545 case INSTR_ADDR_STR: a64asm->ADDR_STR(test.cond, Rd,Rn,op2); break;
546 default: printf("Error"); return;
547 }
548 a64asm->epilog(0);
549 flushcache();
550
551 asm_function_t asm_function = (asm_function_t)(instrMem);
552
553 for(i = 0; i < NUM_REGS; ++i)
554 savedRegs[i] = regs[i];
555
556 asm_mips_test_jacket(asm_function, regs, flags);
557
558 /* Check if all regs except Rd/Rn are same */
559 for(i = 0; i < NUM_REGS; ++i)
560 {
561 if(i == Rd || i == Rn || i == R_v0) continue;
562
563 if(regs[i] != savedRegs[i])
564 {
565 printf("Test %x failed Reg(%d) tampered"
566 " Expected(0x%" PRIx64 "), Actual(0x%" PRIx64 ") t\n",
567 test.id, i, savedRegs[i], regs[i]);
568 return;
569 }
570 }
571
572 if((uint64_t)regs[Rd] != test.postRdValue)
573 {
574 printf("Test %x failed, "
575 "Expected in Rd(0x%" PRIx64 "), Actual(0x%" PRIx64 ")\n",
576 test.id, test.postRdValue, regs[Rd]);
577 }
578 else if((uint64_t)regs[Rn] != (uint64_t)(&dataMem[test.postRnValue]))
579 {
580 printf("Test %x failed, "
581 "Expected in Rn(0x%" PRIx64 "), Actual(0x%" PRIx64 ")\n",
582 test.id, test.postRnValue, regs[Rn] - (uint64_t)dataMem);
583 }
584 else if(test.checkMem == true)
585 {
586 unsigned char *addr = (unsigned char *)&dataMem[test.postMemOffset];
587 uint64_t value;
588 value = 0;
589 for(uint32_t j = 0; j < test.postMemLength; ++j)
590 value = (value << 8) | addr[test.postMemLength-j-1];
591 if(value != test.postMemValue)
592 {
593 printf("Test %x failed, "
594 "Expected in Mem(0x%" PRIx64 "), Actual(0x%" PRIx64 ")\n",
595 test.id, test.postMemValue, value);
596 }
597 else
598 {
599 printf("Test %x passed\n", test.id);
600 }
601 }
602 else
603 {
604 printf("Test %x passed\n", test.id);
605 }
606 }
607
main(void)608 int main(void)
609 {
610 uint32_t i;
611
612 /* Allocate memory to store instructions generated by ArmToArm64Assembler */
613 {
614 int fd = ashmem_create_region("code cache", instrMemSize);
615 if(fd < 0) {
616 printf("IF < 0\n");
617 printf("Creating code cache, ashmem_create_region "
618 "failed with error '%s'", strerror(errno));
619 }
620 instrMem = mmap(NULL, instrMemSize,
621 PROT_READ | PROT_WRITE | PROT_EXEC,
622 MAP_PRIVATE, fd, 0);
623 }
624
625 ArmToMips64Assembler a64asm(instrMem);
626
627 if(TESTS_DATAOP_ENABLE)
628 {
629 printf("Running data processing tests\n");
630 for(i = 0; i < sizeof(dataOpTests)/sizeof(dataOpTest_t); ++i) {
631 dataOpTest(dataOpTests[i], &a64asm);
632 }
633 }
634
635 if(TESTS_DATATRANSFER_ENABLE)
636 {
637 printf("Running data transfer tests\n");
638 for(i = 0; i < sizeof(dataTransferTests)/sizeof(dataTransferTest_t); ++i)
639 dataTransferTest(dataTransferTests[i], &a64asm);
640 }
641
642 return 0;
643 }
644