Lines Matching defs:rd
99 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, in EmitR()
113 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, in EmitRsd()
126 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, in EmitRtd()
303 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Addu()
311 void Mips64Assembler::Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Daddu()
319 void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Subu()
323 void Mips64Assembler::Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dsubu()
327 void Mips64Assembler::MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in MulR6()
331 void Mips64Assembler::MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in MuhR6()
335 void Mips64Assembler::DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in DivR6()
339 void Mips64Assembler::ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in ModR6()
343 void Mips64Assembler::DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in DivuR6()
347 void Mips64Assembler::ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in ModuR6()
351 void Mips64Assembler::Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmul()
355 void Mips64Assembler::Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmuh()
359 void Mips64Assembler::Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Ddiv()
363 void Mips64Assembler::Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmod()
367 void Mips64Assembler::Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Ddivu()
371 void Mips64Assembler::Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmodu()
375 void Mips64Assembler::And(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in And()
383 void Mips64Assembler::Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Or()
391 void Mips64Assembler::Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Xor()
399 void Mips64Assembler::Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Nor()
403 void Mips64Assembler::Bitswap(GpuRegister rd, GpuRegister rt) { in Bitswap()
407 void Mips64Assembler::Dbitswap(GpuRegister rd, GpuRegister rt) { in Dbitswap()
411 void Mips64Assembler::Seb(GpuRegister rd, GpuRegister rt) { in Seb()
415 void Mips64Assembler::Seh(GpuRegister rd, GpuRegister rt) { in Seh()
419 void Mips64Assembler::Dsbh(GpuRegister rd, GpuRegister rt) { in Dsbh()
423 void Mips64Assembler::Dshd(GpuRegister rd, GpuRegister rt) { in Dshd()
440 void Mips64Assembler::Lsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne) { in Lsa()
446 void Mips64Assembler::Dlsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne) { in Dlsa()
452 void Mips64Assembler::Wsbh(GpuRegister rd, GpuRegister rt) { in Wsbh()
476 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) { in Sll()
480 void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) { in Srl()
484 void Mips64Assembler::Rotr(GpuRegister rd, GpuRegister rt, int shamt) { in Rotr()
488 void Mips64Assembler::Sra(GpuRegister rd, GpuRegister rt, int shamt) { in Sra()
492 void Mips64Assembler::Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Sllv()
496 void Mips64Assembler::Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Rotrv()
500 void Mips64Assembler::Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Srlv()
504 void Mips64Assembler::Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Srav()
508 void Mips64Assembler::Dsll(GpuRegister rd, GpuRegister rt, int shamt) { in Dsll()
512 void Mips64Assembler::Dsrl(GpuRegister rd, GpuRegister rt, int shamt) { in Dsrl()
516 void Mips64Assembler::Drotr(GpuRegister rd, GpuRegister rt, int shamt) { in Drotr()
520 void Mips64Assembler::Dsra(GpuRegister rd, GpuRegister rt, int shamt) { in Dsra()
524 void Mips64Assembler::Dsll32(GpuRegister rd, GpuRegister rt, int shamt) { in Dsll32()
528 void Mips64Assembler::Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) { in Dsrl32()
532 void Mips64Assembler::Drotr32(GpuRegister rd, GpuRegister rt, int shamt) { in Drotr32()
536 void Mips64Assembler::Dsra32(GpuRegister rd, GpuRegister rt, int shamt) { in Dsra32()
540 void Mips64Assembler::Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Dsllv()
544 void Mips64Assembler::Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Dsrlv()
548 void Mips64Assembler::Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Drotrv()
552 void Mips64Assembler::Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Dsrav()
641 void Mips64Assembler::Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Slt()
645 void Mips64Assembler::Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Sltu()
657 void Mips64Assembler::Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Seleqz()
661 void Mips64Assembler::Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Selnez()
665 void Mips64Assembler::Clz(GpuRegister rd, GpuRegister rs) { in Clz()
669 void Mips64Assembler::Clo(GpuRegister rd, GpuRegister rs) { in Clo()
673 void Mips64Assembler::Dclz(GpuRegister rd, GpuRegister rs) { in Dclz()
677 void Mips64Assembler::Dclo(GpuRegister rd, GpuRegister rs) { in Dclo()
681 void Mips64Assembler::Jalr(GpuRegister rd, GpuRegister rs) { in Jalr()
1187 void Mips64Assembler::Move(GpuRegister rd, GpuRegister rs) { in Move()
1191 void Mips64Assembler::Clear(GpuRegister rd) { in Clear()
1195 void Mips64Assembler::Not(GpuRegister rd, GpuRegister rs) { in Not()
1909 void Mips64Assembler::LoadConst32(GpuRegister rd, int32_t value) { in LoadConst32()
1917 void Mips64Assembler::LoadConst64(GpuRegister rd, int64_t value) { in LoadConst64()