Lines Matching refs:surf_man
98 typedef int (*hw_init_surface_t)(struct radeon_surface_manager *surf_man,
100 typedef int (*hw_best_surface_t)(struct radeon_surface_manager *surf_man,
140 static int radeon_get_family(struct radeon_surface_manager *surf_man) in radeon_get_family() argument
142 switch (surf_man->device_id) { in radeon_get_family()
143 #define CHIPSET(pci_id, name, fam) case pci_id: surf_man->family = CHIP_##fam; break; in radeon_get_family()
203 static int r6_init_hw_info(struct radeon_surface_manager *surf_man) in r6_init_hw_info() argument
209 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG, in r6_init_hw_info()
215 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
216 version = drmGetVersion(surf_man->fd); in r6_init_hw_info()
218 surf_man->hw_info.allow_2d = 1; in r6_init_hw_info()
224 surf_man->hw_info.num_pipes = 1; in r6_init_hw_info()
227 surf_man->hw_info.num_pipes = 2; in r6_init_hw_info()
230 surf_man->hw_info.num_pipes = 4; in r6_init_hw_info()
233 surf_man->hw_info.num_pipes = 8; in r6_init_hw_info()
236 surf_man->hw_info.num_pipes = 8; in r6_init_hw_info()
237 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
243 surf_man->hw_info.num_banks = 4; in r6_init_hw_info()
246 surf_man->hw_info.num_banks = 8; in r6_init_hw_info()
249 surf_man->hw_info.num_banks = 8; in r6_init_hw_info()
250 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
256 surf_man->hw_info.group_bytes = 256; in r6_init_hw_info()
259 surf_man->hw_info.group_bytes = 512; in r6_init_hw_info()
262 surf_man->hw_info.group_bytes = 256; in r6_init_hw_info()
263 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
269 static int r6_surface_init_linear(struct radeon_surface_manager *surf_man, in r6_surface_init_linear() argument
278 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_linear()
283 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear()
303 static int r6_surface_init_linear_aligned(struct radeon_surface_manager *surf_man, in r6_surface_init_linear_aligned() argument
312 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_linear_aligned()
314 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear_aligned()
331 static int r6_surface_init_1d(struct radeon_surface_manager *surf_man, in r6_surface_init_1d() argument
340 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples); in r6_surface_init_1d()
348 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_1d()
364 static int r6_surface_init_2d(struct radeon_surface_manager *surf_man, in r6_surface_init_2d() argument
374 xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) / in r6_surface_init_2d()
376 xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign); in r6_surface_init_2d()
379 yalign = tilew * surf_man->hw_info.num_pipes; in r6_surface_init_2d()
385 MAX2(surf_man->hw_info.num_pipes * in r6_surface_init_2d()
386 surf_man->hw_info.num_banks * in r6_surface_init_2d()
396 return r6_surface_init_1d(surf_man, surf, offset, i); in r6_surface_init_2d()
407 static int r6_surface_init(struct radeon_surface_manager *surf_man, in r6_surface_init() argument
437 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) { in r6_surface_init()
460 r = r6_surface_init_linear(surf_man, surf, 0, 0); in r6_surface_init()
463 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0); in r6_surface_init()
466 r = r6_surface_init_1d(surf_man, surf, 0, 0); in r6_surface_init()
469 r = r6_surface_init_2d(surf_man, surf, 0, 0); in r6_surface_init()
477 static int r6_surface_best(struct radeon_surface_manager *surf_man, in r6_surface_best() argument
488 static int eg_init_hw_info(struct radeon_surface_manager *surf_man) in eg_init_hw_info() argument
494 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG, in eg_init_hw_info()
500 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
501 version = drmGetVersion(surf_man->fd); in eg_init_hw_info()
503 surf_man->hw_info.allow_2d = 1; in eg_init_hw_info()
509 surf_man->hw_info.num_pipes = 1; in eg_init_hw_info()
512 surf_man->hw_info.num_pipes = 2; in eg_init_hw_info()
515 surf_man->hw_info.num_pipes = 4; in eg_init_hw_info()
518 surf_man->hw_info.num_pipes = 8; in eg_init_hw_info()
521 surf_man->hw_info.num_pipes = 8; in eg_init_hw_info()
522 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
528 surf_man->hw_info.num_banks = 4; in eg_init_hw_info()
531 surf_man->hw_info.num_banks = 8; in eg_init_hw_info()
534 surf_man->hw_info.num_banks = 16; in eg_init_hw_info()
537 surf_man->hw_info.num_banks = 8; in eg_init_hw_info()
538 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
544 surf_man->hw_info.group_bytes = 256; in eg_init_hw_info()
547 surf_man->hw_info.group_bytes = 512; in eg_init_hw_info()
550 surf_man->hw_info.group_bytes = 256; in eg_init_hw_info()
551 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
557 surf_man->hw_info.row_size = 1024; in eg_init_hw_info()
560 surf_man->hw_info.row_size = 2048; in eg_init_hw_info()
563 surf_man->hw_info.row_size = 4096; in eg_init_hw_info()
566 surf_man->hw_info.row_size = 4096; in eg_init_hw_info()
567 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
614 static int eg_surface_init_1d(struct radeon_surface_manager *surf_man, in eg_surface_init_1d() argument
625 xalign = surf_man->hw_info.group_bytes / (tilew * bpe * surf->nsamples); in eg_surface_init_1d()
634 unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes); in eg_surface_init_1d()
655 static int eg_surface_init_2d(struct radeon_surface_manager *surf_man, in eg_surface_init_2d() argument
678 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea; in eg_surface_init_2d()
679 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea; in eg_surface_init_2d()
697 return eg_surface_init_1d(surf_man, surf, level, bpe, offset, i); in eg_surface_init_2d()
708 static int eg_surface_sanity(struct radeon_surface_manager *surf_man, in eg_surface_sanity() argument
725 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) { in eg_surface_sanity()
759 if (surf_man->hw_info.num_banks < surf->mtilea) { in eg_surface_sanity()
783 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) { in eg_surface_sanity()
791 static int eg_surface_init_1d_miptrees(struct radeon_surface_manager *surf_man, in eg_surface_init_1d_miptrees() argument
801 r = eg_surface_init_1d(surf_man, surf, surf->level, surf->bpe, 0, 0); in eg_surface_init_1d_miptrees()
806 r = eg_surface_init_1d(surf_man, surf, stencil_level, 1, in eg_surface_init_1d_miptrees()
813 static int eg_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man, in eg_surface_init_2d_miptrees() argument
823 r = eg_surface_init_2d(surf_man, surf, surf->level, surf->bpe, in eg_surface_init_2d_miptrees()
829 r = eg_surface_init_2d(surf_man, surf, stencil_level, 1, in eg_surface_init_2d_miptrees()
836 static int eg_surface_init(struct radeon_surface_manager *surf_man, in eg_surface_init() argument
865 r = eg_surface_sanity(surf_man, surf, mode); in eg_surface_init()
876 r = r6_surface_init_linear(surf_man, surf, 0, 0); in eg_surface_init()
879 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0); in eg_surface_init()
882 r = eg_surface_init_1d_miptrees(surf_man, surf); in eg_surface_init()
885 r = eg_surface_init_2d_miptrees(surf_man, surf); in eg_surface_init()
911 static int eg_surface_best(struct radeon_surface_manager *surf_man, in eg_surface_best() argument
924 surf->mtilea = surf_man->hw_info.num_banks; in eg_surface_best()
927 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
935 r = eg_surface_sanity(surf_man, surf, mode); in eg_surface_best()
977 surf->tile_split = surf_man->hw_info.row_size; in eg_surface_best()
978 surf->stencil_tile_split = surf_man->hw_info.row_size / 2; in eg_surface_best()
1016 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
1021 h_over_w = (((surf->bankh * surf_man->hw_info.num_banks) << 16) / in eg_surface_best()
1022 (surf->bankw * surf_man->hw_info.num_pipes)) >> 16; in eg_surface_best()
1202 static int si_init_hw_info(struct radeon_surface_manager *surf_man) in si_init_hw_info() argument
1208 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG, in si_init_hw_info()
1214 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1215 version = drmGetVersion(surf_man->fd); in si_init_hw_info()
1217 …if (!radeon_get_value(surf_man->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, surf_man->hw_info.tile_mode_ar… in si_init_hw_info()
1218 surf_man->hw_info.allow_2d = 1; in si_init_hw_info()
1225 surf_man->hw_info.num_pipes = 1; in si_init_hw_info()
1228 surf_man->hw_info.num_pipes = 2; in si_init_hw_info()
1231 surf_man->hw_info.num_pipes = 4; in si_init_hw_info()
1234 surf_man->hw_info.num_pipes = 8; in si_init_hw_info()
1237 surf_man->hw_info.num_pipes = 8; in si_init_hw_info()
1238 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1244 surf_man->hw_info.num_banks = 4; in si_init_hw_info()
1247 surf_man->hw_info.num_banks = 8; in si_init_hw_info()
1250 surf_man->hw_info.num_banks = 16; in si_init_hw_info()
1253 surf_man->hw_info.num_banks = 8; in si_init_hw_info()
1254 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1260 surf_man->hw_info.group_bytes = 256; in si_init_hw_info()
1263 surf_man->hw_info.group_bytes = 512; in si_init_hw_info()
1266 surf_man->hw_info.group_bytes = 256; in si_init_hw_info()
1267 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1273 surf_man->hw_info.row_size = 1024; in si_init_hw_info()
1276 surf_man->hw_info.row_size = 2048; in si_init_hw_info()
1279 surf_man->hw_info.row_size = 4096; in si_init_hw_info()
1282 surf_man->hw_info.row_size = 4096; in si_init_hw_info()
1283 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1289 static int si_surface_sanity(struct radeon_surface_manager *surf_man, in si_surface_sanity() argument
1307 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) { in si_surface_sanity()
1350 gb_tile_mode = surf_man->hw_info.tile_mode_array[*stencil_tile_mode]; in si_surface_sanity()
1401 gb_tile_mode = surf_man->hw_info.tile_mode_array[*tile_mode]; in si_surface_sanity()
1520 static int si_surface_init_linear_aligned(struct radeon_surface_manager *surf_man, in si_surface_init_linear_aligned() argument
1530 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in si_surface_init_linear_aligned()
1535 slice_align = MAX2(64 * surf->bpe, surf_man->hw_info.group_bytes); in si_surface_init_linear_aligned()
1553 static int si_surface_init_1d(struct radeon_surface_manager *surf_man, in si_surface_init_1d() argument
1560 unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes); in si_surface_init_1d()
1567 slice_align = surf_man->hw_info.group_bytes; in si_surface_init_1d()
1602 static int si_surface_init_1d_miptrees(struct radeon_surface_manager *surf_man, in si_surface_init_1d_miptrees() argument
1608 r = si_surface_init_1d(surf_man, surf, surf->level, surf->bpe, tile_mode, 0, 0); in si_surface_init_1d_miptrees()
1614 …r = si_surface_init_1d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, surf->bo_size, 0… in si_surface_init_1d_miptrees()
1620 static int si_surface_init_2d(struct radeon_surface_manager *surf_man, in si_surface_init_2d() argument
1684 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i); in si_surface_init_2d()
1704 static int si_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man, in si_surface_init_2d_miptrees() argument
1713 gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode]; in si_surface_init_2d_miptrees()
1716 …r = si_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, num_pipes, num_banks, su… in si_surface_init_2d_miptrees()
1722 …r = si_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, num_pipes, num_b… in si_surface_init_2d_miptrees()
1728 static int si_surface_init(struct radeon_surface_manager *surf_man, in si_surface_init() argument
1757 r = si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in si_surface_init()
1768 r = r6_surface_init_linear(surf_man, surf, 0, 0); in si_surface_init()
1771 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0); in si_surface_init()
1774 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in si_surface_init()
1777 r = si_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in si_surface_init()
1788 static int si_surface_best(struct radeon_surface_manager *surf_man, in si_surface_best() argument
1803 return si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in si_surface_best()
1860 static void cik_get_2d_params(struct radeon_surface_manager *surf_man, in cik_get_2d_params() argument
1870 uint32_t gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode]; in cik_get_2d_params()
1948 tile_split = MIN2(surf_man->hw_info.row_size, tile_split); in cik_get_2d_params()
1956 gb_macrotile_mode = surf_man->hw_info.macrotile_mode_array[macrotile_index]; in cik_get_2d_params()
2031 static int cik_init_hw_info(struct radeon_surface_manager *surf_man) in cik_init_hw_info() argument
2037 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG, in cik_init_hw_info()
2043 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2044 version = drmGetVersion(surf_man->fd); in cik_init_hw_info()
2046 …if (!radeon_get_value(surf_man->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, surf_man->hw_info.tile_mode_ar… in cik_init_hw_info()
2047 …!radeon_get_value(surf_man->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, surf_man->hw_info.macrotile_… in cik_init_hw_info()
2048 surf_man->hw_info.allow_2d = 1; in cik_init_hw_info()
2055 surf_man->hw_info.num_pipes = 1; in cik_init_hw_info()
2058 surf_man->hw_info.num_pipes = 2; in cik_init_hw_info()
2061 surf_man->hw_info.num_pipes = 4; in cik_init_hw_info()
2064 surf_man->hw_info.num_pipes = 8; in cik_init_hw_info()
2067 surf_man->hw_info.num_pipes = 8; in cik_init_hw_info()
2068 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2074 surf_man->hw_info.num_banks = 4; in cik_init_hw_info()
2077 surf_man->hw_info.num_banks = 8; in cik_init_hw_info()
2080 surf_man->hw_info.num_banks = 16; in cik_init_hw_info()
2083 surf_man->hw_info.num_banks = 8; in cik_init_hw_info()
2084 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2090 surf_man->hw_info.group_bytes = 256; in cik_init_hw_info()
2093 surf_man->hw_info.group_bytes = 512; in cik_init_hw_info()
2096 surf_man->hw_info.group_bytes = 256; in cik_init_hw_info()
2097 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2103 surf_man->hw_info.row_size = 1024; in cik_init_hw_info()
2106 surf_man->hw_info.row_size = 2048; in cik_init_hw_info()
2109 surf_man->hw_info.row_size = 4096; in cik_init_hw_info()
2112 surf_man->hw_info.row_size = 4096; in cik_init_hw_info()
2113 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2119 static int cik_surface_sanity(struct radeon_surface_manager *surf_man, in cik_surface_sanity() argument
2135 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) { in cik_surface_sanity()
2179 cik_get_2d_params(surf_man, 1, surf->nsamples, false, in cik_surface_sanity()
2191 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples, in cik_surface_sanity()
2217 static int cik_surface_init_2d(struct radeon_surface_manager *surf_man, in cik_surface_init_2d() argument
2237 tile_split = MIN2(surf_man->hw_info.row_size, tile_split); in cik_surface_init_2d()
2286 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i); in cik_surface_init_2d()
2306 static int cik_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man, in cik_surface_init_2d_miptrees() argument
2313 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples, in cik_surface_init_2d_miptrees()
2317 r = cik_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, in cik_surface_init_2d_miptrees()
2324 r = cik_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, in cik_surface_init_2d_miptrees()
2332 static int cik_surface_init(struct radeon_surface_manager *surf_man, in cik_surface_init() argument
2361 r = cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in cik_surface_init()
2372 r = r6_surface_init_linear(surf_man, surf, 0, 0); in cik_surface_init()
2375 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0); in cik_surface_init()
2378 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in cik_surface_init()
2381 r = cik_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in cik_surface_init()
2392 static int cik_surface_best(struct radeon_surface_manager *surf_man, in cik_surface_best() argument
2407 return cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in cik_surface_best()
2417 struct radeon_surface_manager *surf_man; in radeon_surface_manager_new() local
2419 surf_man = calloc(1, sizeof(struct radeon_surface_manager)); in radeon_surface_manager_new()
2420 if (surf_man == NULL) { in radeon_surface_manager_new()
2423 surf_man->fd = fd; in radeon_surface_manager_new()
2424 if (radeon_get_value(fd, RADEON_INFO_DEVICE_ID, &surf_man->device_id)) { in radeon_surface_manager_new()
2427 if (radeon_get_family(surf_man)) { in radeon_surface_manager_new()
2431 if (surf_man->family <= CHIP_RV740) { in radeon_surface_manager_new()
2432 if (r6_init_hw_info(surf_man)) { in radeon_surface_manager_new()
2435 surf_man->surface_init = &r6_surface_init; in radeon_surface_manager_new()
2436 surf_man->surface_best = &r6_surface_best; in radeon_surface_manager_new()
2437 } else if (surf_man->family <= CHIP_ARUBA) { in radeon_surface_manager_new()
2438 if (eg_init_hw_info(surf_man)) { in radeon_surface_manager_new()
2441 surf_man->surface_init = &eg_surface_init; in radeon_surface_manager_new()
2442 surf_man->surface_best = &eg_surface_best; in radeon_surface_manager_new()
2443 } else if (surf_man->family < CHIP_BONAIRE) { in radeon_surface_manager_new()
2444 if (si_init_hw_info(surf_man)) { in radeon_surface_manager_new()
2447 surf_man->surface_init = &si_surface_init; in radeon_surface_manager_new()
2448 surf_man->surface_best = &si_surface_best; in radeon_surface_manager_new()
2450 if (cik_init_hw_info(surf_man)) { in radeon_surface_manager_new()
2453 surf_man->surface_init = &cik_surface_init; in radeon_surface_manager_new()
2454 surf_man->surface_best = &cik_surface_best; in radeon_surface_manager_new()
2457 return surf_man; in radeon_surface_manager_new()
2459 free(surf_man); in radeon_surface_manager_new()
2464 radeon_surface_manager_free(struct radeon_surface_manager *surf_man) in radeon_surface_manager_free() argument
2466 free(surf_man); in radeon_surface_manager_free()
2469 static int radeon_surface_sanity(struct radeon_surface_manager *surf_man, in radeon_surface_sanity() argument
2474 if (surf_man == NULL || surf_man->surface_init == NULL || surf == NULL) { in radeon_surface_sanity()
2516 if (surf_man->family >= CHIP_RV770) { in radeon_surface_sanity()
2537 radeon_surface_init(struct radeon_surface_manager *surf_man, in radeon_surface_init() argument
2546 r = radeon_surface_sanity(surf_man, surf, type, mode); in radeon_surface_init()
2550 return surf_man->surface_init(surf_man, surf); in radeon_surface_init()
2554 radeon_surface_best(struct radeon_surface_manager *surf_man, in radeon_surface_best() argument
2563 r = radeon_surface_sanity(surf_man, surf, type, mode); in radeon_surface_best()
2567 return surf_man->surface_best(surf_man, surf); in radeon_surface_best()