Lines Matching refs:SU
283 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDataDeps() argument
284 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
295 SUnit *UseSU = I->SU; in addPhysRegDataDeps()
296 if (UseSU == SU) in addPhysRegDataDeps()
305 Dep = SDep(SU, SDep::Artificial); in addPhysRegDataDeps()
309 SU->hasPhysRegDefs = true; in addPhysRegDataDeps()
310 Dep = SDep(SU, SDep::Data, *Alias); in addPhysRegDataDeps()
314 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse, in addPhysRegDataDeps()
317 ST.adjustSchedDependency(SU, UseSU, Dep); in addPhysRegDataDeps()
326 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDeps() argument
327 MachineInstr *MI = SU->getInstr(); in addPhysRegDeps()
342 SUnit *DefSU = I->SU; in addPhysRegDeps()
345 if (DefSU != SU && in addPhysRegDeps()
349 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias)); in addPhysRegDeps()
351 SDep Dep(SU, Kind, /*Reg=*/*Alias); in addPhysRegDeps()
361 SU->hasPhysRegUses = true; in addPhysRegDeps()
365 Uses.insert(PhysRegSUOper(SU, OperIdx, MO.getReg())); in addPhysRegDeps()
370 addPhysRegDataDeps(SU, OperIdx); in addPhysRegDeps()
379 } else if (SU->isCall) { in addPhysRegDeps()
390 if (!I->SU->isCall) in addPhysRegDeps()
397 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg)); in addPhysRegDeps()
421 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) { in addVRegDefDeps() argument
422 MachineInstr *MI = SU->getInstr(); in addVRegDefDeps()
459 SUnit *UseSU = I->SU; in addVRegDefDeps()
461 SDep Dep(SU, SDep::Data, Reg); in addVRegDefDeps()
464 ST.adjustSchedDependency(SU, UseSU, Dep); in addVRegDefDeps()
496 SUnit *DefSU = V2SU.SU; in addVRegDefDeps()
502 if (DefSU == SU) in addVRegDefDeps()
504 SDep Dep(SU, SDep::Output, Reg); in addVRegDefDeps()
514 V2SU.SU = SU; in addVRegDefDeps()
521 CurrentVRegDefs.insert(VReg2SUnit(Reg, LaneMask, SU)); in addVRegDefDeps()
530 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) { in addVRegUseDeps() argument
531 const MachineInstr *MI = SU->getInstr(); in addVRegUseDeps()
537 CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU)); in addVRegUseDeps()
546 if (V2SU.SU == SU) in addVRegUseDeps()
549 V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg)); in addVRegUseDeps()
652 SUnit *SU = newSUnit(&MI); in initSUnits() local
653 MISUnitMap[&MI] = SU; in initSUnits()
655 SU->isCall = MI.isCall(); in initSUnits()
656 SU->isCommutable = MI.isCommutable(); in initSUnits()
659 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr()); in initSUnits()
670 const MCSchedClassDesc *SC = getSchedClass(SU); in initSUnits()
676 SU->hasReservedResource = true; in initSUnits()
679 SU->isUnbuffered = true; in initSUnits()
689 void ScheduleDAGInstrs::collectVRegUses(SUnit *SU) { in collectVRegUses() argument
690 const MachineInstr *MI = SU->getInstr(); in collectVRegUses()
719 if (UI->SU == SU) in collectVRegUses()
723 VRegUses.insert(VReg2SUnit(Reg, 0, SU)); in collectVRegUses()
745 void inline insert(SUnit *SU, ValueType V) { in insert() argument
746 MapVector::operator[](V).push_back(SU); in insert()
783 void ScheduleDAGInstrs::addChainDependencies(SUnit *SU, in addChainDependencies() argument
786 addChainDependencies(SU, I.second, in addChainDependencies()
790 void ScheduleDAGInstrs::addChainDependencies(SUnit *SU, in addChainDependencies() argument
795 addChainDependencies(SU, Itr->second, in addChainDependencies()
804 for (auto *SU : sus) in addBarrierChain() local
805 SU->addPredBarrier(BarrierChain); in addBarrierChain()
925 SUnit *SU = MISUnitMap[&MI]; in buildSchedGraph() local
926 assert(SU && "No SUnit mapped to this MI"); in buildSchedGraph()
929 collectVRegUses(SU); in buildSchedGraph()
938 PDiffs->addInstruction(SU->NodeNum, RegOpers, MRI); in buildSchedGraph()
964 addPhysRegDeps(SU, j); in buildSchedGraph()
967 addVRegDefDeps(SU, j); in buildSchedGraph()
984 addPhysRegDeps(SU, j); in buildSchedGraph()
986 addVRegUseDeps(SU, j); in buildSchedGraph()
995 if (SU->NumSuccs == 0 && SU->Latency > 1 && (HasVRegDef || MI.mayLoad())) { in buildSchedGraph()
996 SDep Dep(SU, SDep::Artificial); in buildSchedGraph()
997 Dep.setLatency(SU->Latency - 1); in buildSchedGraph()
1010 BarrierChain->addPredBarrier(SU); in buildSchedGraph()
1011 BarrierChain = SU; in buildSchedGraph()
1031 BarrierChain->addPredBarrier(SU); in buildSchedGraph()
1043 addChainDependencies(SU, Stores); in buildSchedGraph()
1044 addChainDependencies(SU, NonAliasStores); in buildSchedGraph()
1045 addChainDependencies(SU, Loads); in buildSchedGraph()
1046 addChainDependencies(SU, NonAliasLoads); in buildSchedGraph()
1049 Stores.insert(SU, UnknownValue); in buildSchedGraph()
1058 addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V); in buildSchedGraph()
1059 addChainDependencies(SU, (ThisMayAlias ? Loads : NonAliasLoads), V); in buildSchedGraph()
1068 (ThisMayAlias ? Stores : NonAliasStores).insert(SU, V); in buildSchedGraph()
1072 addChainDependencies(SU, Loads, UnknownValue); in buildSchedGraph()
1073 addChainDependencies(SU, Stores, UnknownValue); in buildSchedGraph()
1078 addChainDependencies(SU, Stores); in buildSchedGraph()
1079 addChainDependencies(SU, NonAliasStores); in buildSchedGraph()
1081 Loads.insert(SU, UnknownValue); in buildSchedGraph()
1089 addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V); in buildSchedGraph()
1092 (ThisMayAlias ? Loads : NonAliasLoads).insert(SU, V); in buildSchedGraph()
1095 addChainDependencies(SU, Stores, UnknownValue); in buildSchedGraph()
1158 for (auto *SU : I.second) in reduceHugeMemNodeMaps() local
1159 NodeNums.push_back(SU->NodeNum); in reduceHugeMemNodeMaps()
1161 for (auto *SU : I.second) in reduceHugeMemNodeMaps() local
1162 NodeNums.push_back(SU->NodeNum); in reduceHugeMemNodeMaps()
1371 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const { in dumpNode()
1373 SU->getInstr()->dump(); in dumpNode()
1377 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const { in getGraphNodeLabel()
1380 if (SU == &EntrySU) in getGraphNodeLabel()
1382 else if (SU == &ExitSU) in getGraphNodeLabel()
1385 SU->getInstr()->print(oss, /*SkipOpers=*/true); in getGraphNodeLabel()
1432 bool isVisited(const SUnit *SU) const { in isVisited()
1433 return R.DFSNodeData[SU->NodeNum].SubtreeID in isVisited()
1439 void visitPreorder(const SUnit *SU) { in visitPreorder() argument
1440 R.DFSNodeData[SU->NodeNum].InstrCount = in visitPreorder()
1441 SU->getInstr()->isTransient() ? 0 : 1; in visitPreorder()
1447 void visitPostorderNode(const SUnit *SU) { in visitPostorderNode() argument
1450 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum; in visitPostorderNode()
1451 RootData RData(SU->NodeNum); in visitPostorderNode()
1452 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1; in visitPostorderNode()
1459 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount; in visitPostorderNode()
1461 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) { in visitPostorderNode()
1466 joinPredSubtree(*PI, SU, /*CheckLimit=*/false); in visitPostorderNode()
1473 RootSet[PredNum].ParentNodeID = SU->NodeNum; in visitPostorderNode()
1484 RootSet[SU->NodeNum] = RData; in visitPostorderNode()
1599 void follow(const SUnit *SU) { in follow() argument
1600 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin())); in follow()
1619 static bool hasDataSucc(const SUnit *SU) { in hasDataSucc() argument
1621 SI = SU->Succs.begin(), SE = SU->Succs.end(); SI != SE; ++SI) { in hasDataSucc()
1637 const SUnit *SU = &*SI; in compute() local
1638 if (Impl.isVisited(SU) || hasDataSucc(SU)) in compute()
1642 Impl.visitPreorder(SU); in compute()
1643 DFS.follow(SU); in compute()