Lines Matching defs:Op0IsKill

428   bool Op0IsKill = hasTrivialKill(I->getOperand(0));
449                                       Op0IsKill, Imm, VT.getSimpleVT());
461                                      ISDOpcode, Op0, Op0IsKill, CF);
476                                    ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill);
1301   bool Op0IsKill = hasTrivialKill(I->getOperand(0));
1318     ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1702                               bool /*Op0IsKill*/) {
1707                                bool /*Op0IsKill*/, unsigned /*Op1*/,
1722                                bool /*Op0IsKill*/, uint64_t /*Imm*/) {
1727                                bool /*Op0IsKill*/,
1733                                 bool /*Op0IsKill*/, unsigned /*Op1*/,
1743                                 bool Op0IsKill, uint64_t Imm, MVT ImmType) {
1761   unsigned ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1782   return fastEmit_rr(VT, VT, Opcode, Op0, Op0IsKill, MaterialReg, IsImmKill);
1817                                   bool Op0IsKill) {
1825         .addReg(Op0, getKillRegState(Op0IsKill));
1828         .addReg(Op0, getKillRegState(Op0IsKill));
1838                                    bool Op0IsKill, unsigned Op1,
1848         .addReg(Op0, getKillRegState(Op0IsKill))
1852         .addReg(Op0, getKillRegState(Op0IsKill))
1862                                     bool Op0IsKill, unsigned Op1,
1874         .addReg(Op0, getKillRegState(Op0IsKill))
1879         .addReg(Op0, getKillRegState(Op0IsKill))
1890                                    bool Op0IsKill, uint64_t Imm) {
1898         .addReg(Op0, getKillRegState(Op0IsKill))
1902         .addReg(Op0, getKillRegState(Op0IsKill))
1912                                     bool Op0IsKill, uint64_t Imm1,
1921         .addReg(Op0, getKillRegState(Op0IsKill))
1926         .addReg(Op0, getKillRegState(Op0IsKill))
1956                                     bool Op0IsKill, unsigned Op1,
1966         .addReg(Op0, getKillRegState(Op0IsKill))
1971         .addReg(Op0, getKillRegState(Op0IsKill))
1997                                               bool Op0IsKill, uint32_t Idx) {
2004           ResultReg).addReg(Op0, getKillRegState(Op0IsKill), Idx);
2010 unsigned FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
2011   return fastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);