Lines Matching refs:Op1IsKill
412 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); in selectBinaryOp() local
415 fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, Op1IsKill, in selectBinaryOp()
472 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); in selectBinaryOp() local
476 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill); in selectBinaryOp()
1839 bool Op1IsKill) { in fastEmitInst_rr() argument
1849 .addReg(Op1, getKillRegState(Op1IsKill)); in fastEmitInst_rr()
1853 .addReg(Op1, getKillRegState(Op1IsKill)); in fastEmitInst_rr()
1863 bool Op1IsKill, unsigned Op2, in fastEmitInst_rrr() argument
1875 .addReg(Op1, getKillRegState(Op1IsKill)) in fastEmitInst_rrr()
1880 .addReg(Op1, getKillRegState(Op1IsKill)) in fastEmitInst_rrr()
1957 bool Op1IsKill, uint64_t Imm) { in fastEmitInst_rri() argument
1967 .addReg(Op1, getKillRegState(Op1IsKill)) in fastEmitInst_rri()
1972 .addReg(Op1, getKillRegState(Op1IsKill)) in fastEmitInst_rri()