Lines Matching refs:getSUnit

141   SUnit *PredSU = PredEdge->getSUnit();  in ReleasePred()
173         LiveRegDefs[I->getReg()] = I->getSUnit();  in ReleasePredecessors()
197       if (LiveRegCycles[I->getReg()] == I->getSUnit()->getHeight()) {  in ScheduleNodeBottomUp()
289       else if (I->getSUnit()->getNode() &&  in CopyAndMoveSuccessors()
290                I->getSUnit()->getNode()->isOperandOf(LoadNode))  in CopyAndMoveSuccessors()
303     if (ChainPred.getSUnit()) {  in CopyAndMoveSuccessors()
322       SUnit *SuccDep = D.getSUnit();  in CopyAndMoveSuccessors()
330       SUnit *SuccDep = D.getSUnit();  in CopyAndMoveSuccessors()
369     SUnit *SuccSU = I->getSUnit();  in CopyAndMoveSuccessors()
406     SUnit *SuccSU = I->getSUnit();  in InsertCopiesAndMoveSuccs()
485       CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs,  in DelayForLiveRegsBottomUp()