200     Topo.AddPred(SU, D.getSUnit());  in AddPred()
208     Topo.RemovePred(SU, D.getSUnit());  in RemovePred()
366   SUnit *PredSU = PredEdge->getSUnit();  in ReleasePred()
536       assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) &&  in ReleasePredecessors()
538       LiveRegDefs[I->getReg()] = I->getSUnit();  in ReleasePredecessors()
792   SUnit *PredSU = PredEdge->getSUnit();  in CapturePred()
814       assert(LiveRegDefs[I->getReg()] == I->getSUnit() &&  in UnscheduleNodeBottomUp()
864         LiveRegGens[Reg] = Succ.getSUnit();  in UnscheduleNodeBottomUp()
867               Succ2.getSUnit()->getHeight() < LiveRegGens[Reg]->getHeight())  in UnscheduleNodeBottomUp()
868             LiveRegGens[Reg] = Succ2.getSUnit();  in UnscheduleNodeBottomUp()
1033       else if (isOperandOf(Pred.getSUnit(), LoadNode))  in CopyAndMoveSuccessors()
1061       SUnit *SuccDep = D.getSUnit();  in CopyAndMoveSuccessors()
1072       SUnit *SuccDep = D.getSUnit();  in CopyAndMoveSuccessors()
1114     SUnit *SuccSU = Succ.getSUnit();  in CopyAndMoveSuccessors()
1153     SUnit *SuccSU = Succ.getSUnit();  in InsertCopiesAndMoveSuccs()
1271       CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs.get(),  in DelayForLiveRegsBottomUp()
1847     SUnit *PredSU = Pred.getSUnit();  in CalcNodeSethiUllmanNumber()
1949     SUnit *PredSU = Pred.getSUnit();  in HighRegPressure()
1998     SUnit *PredSU = Pred.getSUnit();  in RegPressureDiff()
2041     SUnit *PredSU = Pred.getSUnit();  in scheduledNode()
2122     SUnit *PredSU = Pred.getSUnit();  in unscheduledNode()
2189     unsigned Height = Succ.getSUnit()->getHeight();  in closestSucc()
2192     if (Succ.getSUnit()->getNode() &&  in closestSucc()
2193         Succ.getSUnit()->getNode()->getOpcode() == ISD::CopyToReg)  in closestSucc()
2194       Height = closestSucc(Succ.getSUnit())+1;  in closestSucc()
2218     const SUnit *PredSU = Pred.getSUnit();  in hasOnlyLiveInOpers()
2240     const SUnit *SuccSU = Succ.getSUnit();  in hasOnlyLiveOutUses()
2277     Pred.getSUnit()->isVRegCycle = true;  in initVRegCycle()
2289     SUnit *PredSU = Pred.getSUnit();  in resetVRegCycle()
2293       Pred.getSUnit()->isVRegCycle = false;  in resetVRegCycle()
2307     if (Pred.getSUnit()->isVRegCycle &&  in hasVRegCycleUse()
2308         Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {  in hasVRegCycleUse()
2704     SUnit *SuccSU = Succ.getSUnit();  in canClobberReachingPhysRegUse()
2711           scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit()))  in canClobberReachingPhysRegUse()
2720               scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit()))  in canClobberReachingPhysRegUse()
2820         PredSU = Pred.getSUnit();  in PrescheduleNodesWithMultipleUses()
2842       SUnit *PredSuccSU = PredSucc.getSUnit();  in PrescheduleNodesWithMultipleUses()
2865       SUnit *SuccSU = Edge.getSUnit();  in PrescheduleNodesWithMultipleUses()
2912         SUnit *SuccSU = Succ.getSUnit();  in AddPseudoTwoAddrDeps()
2928           SuccSU = SuccSU->Succs.front().getSUnit();  in AddPseudoTwoAddrDeps()