203   unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
205   unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
207   unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
1520 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,  in emitLogicalOp()  argument
1545     ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm);  in emitLogicalOp()
1567       ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitLogicalOp()
1583         ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitLogicalOp()
1596   ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill);  in emitLogicalOp()
1604 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,  in emitLogicalOp_ri()  argument
1624     unsigned Idx = ISDOpc - ISD::AND;  in emitLogicalOp_ri()
1631     Opc = OpcTable[ISDOpc - ISD::AND][1];  in emitLogicalOp_ri()
1643   if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) {  in emitLogicalOp_ri()
1650 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,  in emitLogicalOp_rs()  argument
1675     Opc = OpcTable[ISDOpc - ISD::AND][0];  in emitLogicalOp_rs()
1679     Opc = OpcTable[ISDOpc - ISD::AND][1];  in emitLogicalOp_rs()