Lines Matching refs:LHSReg
161 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
164 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
167 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
172 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
182 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
197 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
199 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
205 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
207 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
210 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
1125 unsigned LHSReg = getRegForValue(LHS); in emitAddSub() local
1126 if (!LHSReg) in emitAddSub()
1131 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1137 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm, in emitAddSub()
1140 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags, in emitAddSub()
1144 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, 0, SetFlags, in emitAddSub()
1160 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1168 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill, in emitAddSub()
1188 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1213 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1231 return emitAddSub_rr(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill, in emitAddSub()
1235 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rr() argument
1239 assert(LHSReg && RHSReg && "Invalid register number."); in emitAddSub_rr()
1261 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1264 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_rr()
1269 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_ri() argument
1272 assert(LHSReg && "Invalid register number."); in emitAddSub_ri()
1306 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1308 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_ri()
1314 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rs() argument
1320 assert(LHSReg && RHSReg && "Invalid register number."); in emitAddSub_rs()
1346 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1349 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_rs()
1355 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rx() argument
1361 assert(LHSReg && RHSReg && "Invalid register number."); in emitAddSub_rx()
1389 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1392 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_rx()
1426 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, in emitICmp_ri() argument
1428 return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, Imm, in emitICmp_ri()
1443 unsigned LHSReg = getRegForValue(LHS); in emitFCmp() local
1444 if (!LHSReg) in emitFCmp()
1451 .addReg(LHSReg, getKillRegState(LHSIsKill)); in emitFCmp()
1462 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitFCmp()
1503 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg, in emitSubs_rr() argument
1506 return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg, in emitSubs_rr()
1510 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg, in emitSubs_rs() argument
1515 return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg, in emitSubs_rs()
1537 unsigned LHSReg = getRegForValue(LHS); in emitLogicalOp() local
1538 if (!LHSReg) in emitLogicalOp()
1545 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm); in emitLogicalOp()
1567 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg, in emitLogicalOp()
1583 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg, in emitLogicalOp()
1596 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill); in emitLogicalOp()
1605 unsigned LHSReg, bool LHSIsKill, in emitLogicalOp_ri() argument
1641 fastEmitInst_ri(Opc, RC, LHSReg, LHSIsKill, in emitLogicalOp_ri()
1651 unsigned LHSReg, bool LHSIsKill, in emitLogicalOp_rs() argument
1684 fastEmitInst_rri(Opc, RC, LHSReg, LHSIsKill, RHSReg, RHSIsKill, in emitLogicalOp_rs()
1693 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, in emitAnd_ri() argument
1695 return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm); in emitAnd_ri()
3582 unsigned LHSReg = getRegForValue(LHS); in fastLowerIntrinsicCall() local
3583 if (!LHSReg) in fastLowerIntrinsicCall()
3593 MulReg = emitSMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill); in fastLowerIntrinsicCall()
3606 MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg, in fastLowerIntrinsicCall()
3608 unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill, in fastLowerIntrinsicCall()
3617 unsigned LHSReg = getRegForValue(LHS); in fastLowerIntrinsicCall() local
3618 if (!LHSReg) in fastLowerIntrinsicCall()
3628 MulReg = emitUMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill); in fastLowerIntrinsicCall()
3638 MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg, in fastLowerIntrinsicCall()
3640 unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill, in fastLowerIntrinsicCall()