188   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1131     LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);  in emitAddSub()
1229     RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);  in emitAddSub()
2274     SrcReg = emitIntExt(VT, SrcReg, MVT::i32, /*IsZExt=*/true);  in emitCompareAndBranch()
2795         emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);  in selectIntToFP()
2963       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);  in processCallArgs()
2973       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);  in processCallArgs()
3749       SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);  in selectRet()
3961       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitLSL_ri()
4068       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitLSR_ri()
4106     Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitLSR_ri()
4151     Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*IsZExt=*/false);  in emitASR_rr()
4189       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitASR_ri()
4244 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,  in emitIntExt()  function in AArch64FastISel
4452   unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);  in selectIntExt()
4830     IdxN = emitIntExt(IdxVT.getSimpleVT(), IdxN, PtrVT, /*IsZExt=*/false);  in getRegForGEPIndex()