1781     SDValue CCVal;  in LowerXOR()  local
1782     SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);  in LowerXOR()
1789                        CCVal, Cmp);  in LowerXOR()
1849   SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);  in LowerXALUO()  local
1851                          CCVal, Overflow);  in LowerXALUO()
3653     SDValue CCVal = DAG.getConstant(OFCC, dl, MVT::i32);  in LowerBR_CC()  local
3655     return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,  in LowerBR_CC()
3718     SDValue CCVal;  in LowerBR_CC()  local
3719     SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);  in LowerBR_CC()
3720     return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,  in LowerBR_CC()
3881     SDValue CCVal;  in LowerSETCC()  local
3883         getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);  in LowerSETCC()
3888     return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);  in LowerSETCC()
4034     SDValue CCVal;  in LowerSELECT_CC()  local
4035     SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);  in LowerSELECT_CC()
4038     return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);  in LowerSELECT_CC()
4078   SDValue CCVal = Op->getOperand(0);  in LowerSELECT()  local
4083   unsigned Opc = CCVal.getOpcode();  in LowerSELECT()
4086   if (CCVal.getResNo() == 1 &&  in LowerSELECT()
4090     if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))  in LowerSELECT()
4095     std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);  in LowerSELECT()
4096     SDValue CCVal = DAG.getConstant(OFCC, DL, MVT::i32);  in LowerSELECT()  local
4099                        CCVal, Overflow);  in LowerSELECT()
4105   if (CCVal.getOpcode() == ISD::SETCC) {  in LowerSELECT()
4106     LHS = CCVal.getOperand(0);  in LowerSELECT()
4107     RHS = CCVal.getOperand(1);  in LowerSELECT()
4108     CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();  in LowerSELECT()
4110     LHS = CCVal;  in LowerSELECT()
4111     RHS = DAG.getConstant(0, DL, CCVal.getValueType());  in LowerSELECT()
4450   SDValue CCVal = DAG.getConstant(AArch64CC::EQ, dl, MVT::i32);  in LowerShiftRightParts()  local
4453                   HiBitsForLo, CCVal, Cmp);  in LowerShiftRightParts()
4464   CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);  in LowerShiftRightParts()
4467                            LoForNormalShift, CCVal, Cmp);  in LowerShiftRightParts()
4478                            HiForNormalShift, CCVal, Cmp);  in LowerShiftRightParts()
4506   SDValue CCVal = DAG.getConstant(AArch64CC::EQ, dl, MVT::i32);  in LowerShiftLeftParts()  local
4509                   LoBitsForHi, CCVal, Cmp);  in LowerShiftLeftParts()
4521   CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);  in LowerShiftLeftParts()
4523                            HiForNormalShift, CCVal, Cmp);  in LowerShiftLeftParts()
4530                            LoForNormalShift, CCVal, Cmp);  in LowerShiftLeftParts()
7513   SDValue CCVal;  in BuildSDIVPow2()  local
7514   SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);  in BuildSDIVPow2()
7516   SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);  in BuildSDIVPow2()
8337   SDValue CCVal;  in performSetccAddFolding()  local
8341     CCVal = DAG.getConstant(  in performSetccAddFolding()
8349                       CCVal, DAG, dl);  in performSetccAddFolding()
8353   return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);  in performSetccAddFolding()
9596   SDValue CCVal = N->getOperand(2);  in performBRCONDCombine()  local
9599   assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");  in performBRCONDCombine()
9600   unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();  in performBRCONDCombine()