743   case AArch64ISD::CSEL: {  in computeKnownBitsForTargetNode()
842   case AArch64ISD::CSEL:              return "AArch64ISD::CSEL";  in getTargetNodeName()
1788     return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,  in LowerXOR()
1850   Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,  in LowerXALUO()
3888     return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);  in LowerSETCC()
3907     return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);  in LowerSETCC()
3917         DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);  in LowerSETCC()
3920     return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);  in LowerSETCC()
3952     unsigned Opcode = AArch64ISD::CSEL;  in LowerSELECT_CC()
4027       if (Opcode != AArch64ISD::CSEL) {  in LowerSELECT_CC()
4052   SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);  in LowerSELECT_CC()
4058     return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);  in LowerSELECT_CC()
4098     return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,  in LowerSELECT()
4452       DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64),  in LowerShiftRightParts()
4466   SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift,  in LowerShiftRightParts()
4477   SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift,  in LowerShiftRightParts()
4508       DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64),  in LowerShiftLeftParts()
4522   SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift,  in LowerShiftLeftParts()
4529   SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift,  in LowerShiftLeftParts()
7473         return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,  in performIntegerAbsCombine()
7516   SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);  in BuildSDIVPow2()
8274   if (Op.getOpcode() != AArch64ISD::CSEL)  in isSetCC()
8353   return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);  in performSetccAddFolding()
9897   case AArch64ISD::CSEL:  in PerformDAGCombine()