Lines Matching refs:GPR32
180 def GPR32as64 : RegisterOperand<GPR32> {
591 def arith_shifted_reg32 : arith_shifted_reg<i32, GPR32, 32>;
613 def logical_shifted_reg32 : logical_shifted_reg<i32, GPR32, logical_shift32>;
708 let MIOperandInfo = (ops GPR32, arith_extend);
714 let MIOperandInfo = (ops GPR32, arith_extend64);
1144 def W : BaseCmpBranch<GPR32, op, asm, node> {
1215 def W : BaseTestBranch<GPR32, tbz_imm0_31_diag, op, asm, node> {
1287 def Wr : BaseOneOperandData<opc, GPR32, asm, node> {
1297 : BaseOneOperandData<opc, GPR32, asm, node> {
1341 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1351 def SWr : BaseAddSubCarrySetFlags<isSub, GPR32, asm_setflags,
1386 def Wr : BaseDiv<isSigned, GPR32, asm, OpNode>,
1404 def Wr : BaseShift<shift_type, GPR32, asm> {
1412 def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)),
1413 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn,
1416 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (zext GPR32:$Rm)))),
1417 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1419 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (anyext GPR32:$Rm)))),
1420 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1422 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (sext GPR32:$Rm)))),
1423 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1450 def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm,
1451 [/*(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))*/]>,
1465 : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
1467 (mul (ExtNode GPR32:$Rn), (ExtNode GPR32:$Rm))))]>,
1494 (inst GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR)>;
1500 (inst GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR)>;
1504 : I<(outs GPR32:$Rd), (ins GPR32:$Rn, StreamReg:$Rm),
1506 [(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>,
1579 def Wi : BaseMoveImmediate<opc, GPR32, movimm32_shift, asm> {
1608 def Wi : BaseInsertImmediate<opc, GPR32, movimm32_shift, asm> {
1753 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1757 def Wrs : BaseAddSubSReg<isSub, 0, GPR32, arith_shifted_reg32, mnemonic,
1796 GPR32, GPR32, GPR32, 0>;
1803 GPR32sponly, GPR32sp, GPR32, 16>; // UXTW #0
1805 GPR32sp, GPR32sponly, GPR32, 16>; // UXTW #0
1818 def Wri : BaseAddSubImm<isSub, 1, GPR32, GPR32sp, addsub_shifted_imm32,
1828 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1832 def Wrs : BaseAddSubSReg<isSub, 1, GPR32, arith_shifted_reg32, mnemonic,
1843 def Wrx : BaseAddSubEReg<isSub, 1, GPR32, GPR32sp,
1863 (!cast<Instruction>(NAME # "Wri") GPR32:$Rd, GPR32sp:$Rn,
1875 WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
1877 XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
1881 WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh), 4>;
1893 WZR, GPR32:$src1, GPR32:$src2, 0), 5>;
1897 WZR, GPR32sponly:$src1, GPR32:$src2, 16), 5>;
1903 GPR32, GPR32, GPR32, 0>;
1910 GPR32, GPR32sponly, GPR32, 16>; // UXTW #0
1942 def Wrri : BaseExtractImm<GPR32, imm0_31, asm,
1943 [(set GPR32:$Rd,
1944 (AArch64Extr GPR32:$Rn, GPR32:$Rm, imm0_31:$imm))]> {
1983 def Wri : BaseBitfieldImm<opc, GPR32, imm0_31, asm> {
2017 def Wri : BaseBitfieldImmWith2RegArgs<opc, GPR32, imm0_31, asm> {
2090 def Wri : BaseLogicalImm<opc, GPR32sp, GPR32, logical_imm32, mnemonic,
2091 [(set GPR32sp:$Rd, (OpNode GPR32:$Rn,
2104 (!cast<Instruction>(NAME # "Wri") GPR32sp:$Rd, GPR32:$Rn,
2114 def Wri : BaseLogicalImm<opc, GPR32, GPR32, logical_imm32, mnemonic,
2115 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_imm32:$imm))]> {
2126 (!cast<Instruction>(NAME # "Wri") GPR32:$Rd, GPR32:$Rn,
2142 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
2146 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
2147 [(set GPR32:$Rd, (OpNode GPR32:$Rn,
2158 !cast<Instruction>(NAME#"Wrs"), GPR32>;
2167 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
2170 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
2171 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_shifted_reg32:$Rm))]> {
2181 !cast<Instruction>(NAME#"Wrs"), GPR32>;
2244 def Wi : BaseCondComparisonImm<op, GPR32, imm32_0_31, mnemonic, OpNode> {
2251 def Wr : BaseCondComparisonReg<op, GPR32, mnemonic, OpNode> {
2286 def Wr : BaseCondSelect<op, op2, GPR32, asm> {
2325 def Wr : BaseCondSelectOp<op, op2, GPR32, asm, frag> {
2332 def : Pat<(AArch64csel (frag GPR32:$Rm), GPR32:$Rn, (i32 imm:$cond), NZCV),
2333 (!cast<Instruction>(NAME # Wr) GPR32:$Rn, GPR32:$Rm,
2607 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2609 (loadop (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2633 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2635 (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2680 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2682 (loadop (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2705 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2707 (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2752 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2754 (loadop (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2777 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2779 (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2824 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2826 (loadop (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2849 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2851 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2896 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2898 (loadop (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2921 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2923 (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2968 (ins prfop:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2970 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
3470 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, (outs GPR32:$Ws),
3488 (outs GPR32:$Ws),
3569 def UWHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR32, asm,
3570 [(set GPR32:$Rd, (OpN FPR16:$Rn))]> {
3583 def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm,
3584 [(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
3595 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
3596 [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3610 def SWHri : BaseFPToInteger<0b11, rmode, opcode, FPR16, GPR32,
3612 [(set GPR32:$Rd, (OpN (fmul FPR16:$Rn,
3629 def SWSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR32,
3631 [(set GPR32:$Rd, (OpN (fmul FPR32:$Rn,
3646 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
3648 [(set GPR32:$Rd, (OpN (fmul FPR64:$Rn,
3704 def UWHri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR16, f16, asm, node> {
3710 def UWSri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR32, f32, asm, node> {
3715 def UWDri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR64, f64, asm, node> {
3737 def SWHri: BaseIntegerToFP<isUnsigned, GPR32, FPR16, fixedpoint_f16_i32, asm,
3739 (fdiv (node GPR32:$Rn),
3747 def SWSri: BaseIntegerToFP<isUnsigned, GPR32, FPR32, fixedpoint_f32_i32, asm,
3749 (fdiv (node GPR32:$Rn),
3756 def SWDri: BaseIntegerToFP<isUnsigned, GPR32, FPR64, fixedpoint_f64_i32, asm,
3758 (fdiv (node GPR32:$Rn),
3860 def WHr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR16, asm> {
3872 def WSr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR32, asm> {
3882 def HWr : BaseUnscaledConversion<0b00, 0b110, FPR16, GPR32, asm> {
3894 def SWr : BaseUnscaledConversion<0b00, 0b110, FPR32, GPR32, asm> {
6184 def vi8to32 : SIMDSMov<0, ".b", GPR32, VectorIndexB> {
6194 def vi16to32 : SIMDSMov<0, ".h", GPR32, VectorIndexH> {
6212 def vi8 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndexB> {
6217 def vi16 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndexH> {
6222 def vi32 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndexS> {
6234 GPR32, VectorIndexS>;
6278 def vi8gpr : SIMDInsFromMain<".b", v16i8, GPR32, VectorIndexB> {
6283 def vi16gpr : SIMDInsFromMain<".h", v8i16, GPR32, VectorIndexH> {
6288 def vi32gpr : SIMDInsFromMain<".s", v4i32, GPR32, VectorIndexS> {
6335 GPR32, VectorIndexB>;
6337 GPR32, VectorIndexH>;
6339 GPR32, VectorIndexS>;
9383 let Sz = 0b00, Acq = Acq, Rel = Rel in def b : BaseCAS<order, "b", GPR32>;
9384 let Sz = 0b01, Acq = Acq, Rel = Rel in def h : BaseCAS<order, "h", GPR32>;
9385 let Sz = 0b10, Acq = Acq, Rel = Rel in def s : BaseCAS<order, "", GPR32>;
9430 let Sz = 0b00, Acq = Acq, Rel = Rel in def b : BaseSWP<order, "b", GPR32>;
9431 let Sz = 0b01, Acq = Acq, Rel = Rel in def h : BaseSWP<order, "h", GPR32>;
9432 let Sz = 0b10, Acq = Acq, Rel = Rel in def s : BaseSWP<order, "", GPR32>;
9464 def b : BaseLDOPregister<op, order, "b", GPR32>;
9466 def h : BaseLDOPregister<op, order, "h", GPR32>;
9468 def s : BaseLDOPregister<op, order, "", GPR32>;
9479 def : BaseSTOPregister<asm # "lb", GPR32, WZR,
9481 def : BaseSTOPregister<asm # "lh", GPR32, WZR,
9483 def : BaseSTOPregister<asm # "l", GPR32, WZR,
9487 def : BaseSTOPregister<asm # "b", GPR32, WZR,
9489 def : BaseSTOPregister<asm # "h", GPR32, WZR,
9491 def : BaseSTOPregister<asm, GPR32, WZR,