Lines Matching refs:GPR64
592 def arith_shifted_reg64 : arith_shifted_reg<i64, GPR64, 64>;
614 def logical_shifted_reg64 : logical_shifted_reg<i64, GPR64, logical_shift64>;
930 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
939 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
1014 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt),
1029 (ins GPR64:$Rt, imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2),
1063 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
1147 def X : BaseCmpBranch<GPR64, op, asm, node> {
1219 def X : BaseTestBranch<GPR64, tbz_imm32_63, op, asm, node> {
1227 def : Pat<(node GPR64:$Rn, tbz_imm0_31_diag:$imm, bb:$target),
1228 (!cast<Instruction>(NAME#"W") (EXTRACT_SUBREG GPR64:$Rn, sub_32),
1291 def Xr : BaseOneOperandData<opc, GPR64, asm, node> {
1302 : BaseOneOperandData<opc, GPR64, asm, node> {
1345 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1356 def SXr : BaseAddSubCarrySetFlags<isSub, GPR64, asm_setflags,
1390 def Xr : BaseDiv<isSigned, GPR64, asm, OpNode>,
1408 def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
1456 def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm,
1457 [/*(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))*/]>,
1465 : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
1466 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
1473 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
1475 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
1497 (inst GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR)>;
1500 (inst GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR)>;
1528 : I<(outs GPR64:$Xd), (ins adr:$label), asm, "\t$Xd, $label", "",
1583 def Xi : BaseMoveImmediate<opc, GPR64, movimm64_shift, asm> {
1612 def Xi : BaseInsertImmediate<opc, GPR64, movimm64_shift, asm> {
1754 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1761 def Xrs : BaseAddSubSReg<isSub, 0, GPR64, arith_shifted_reg64, mnemonic,
1779 def Xrx64 : BaseAddSubEReg64<isSub, 0, GPR64sp, GPR64sp, GPR64,
1798 GPR64, GPR64, GPR64, 0>;
1808 GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0
1811 GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0
1822 def Xri : BaseAddSubImm<isSub, 1, GPR64, GPR64sp, addsub_shifted_imm64,
1829 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1836 def Xrs : BaseAddSubSReg<isSub, 1, GPR64, arith_shifted_reg64, mnemonic,
1847 def Xrx : BaseAddSubEReg<isSub, 1, GPR64, GPR64sp,
1853 def Xrx64 : BaseAddSubEReg64<isSub, 1, GPR64, GPR64sp, GPR64,
1866 (!cast<Instruction>(NAME # "Xri") GPR64:$Rd, GPR64sp:$Rn,
1879 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh), 4>;
1883 XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh), 4>;
1895 XZR, GPR64:$src1, GPR64:$src2, 0), 5>;
1899 XZR, GPR64sponly:$src1, GPR64:$src2, 24), 5>;
1905 GPR64, GPR64, GPR64, 0>;
1913 GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
1950 def Xrri : BaseExtractImm<GPR64, imm0_63, asm,
1951 [(set GPR64:$Rd,
1952 (AArch64Extr GPR64:$Rn, GPR64:$Rm, imm0_63:$imm))]> {
1990 def Xri : BaseBitfieldImm<opc, GPR64, imm0_63, asm> {
2024 def Xri : BaseBitfieldImmWith2RegArgs<opc, GPR64, imm0_63, asm> {
2097 def Xri : BaseLogicalImm<opc, GPR64sp, GPR64, logical_imm64, mnemonic,
2098 [(set GPR64sp:$Rd, (OpNode GPR64:$Rn,
2107 (!cast<Instruction>(NAME # "Xri") GPR64sp:$Rd, GPR64:$Rn,
2119 def Xri : BaseLogicalImm<opc, GPR64, GPR64, logical_imm64, mnemonic,
2120 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_imm64:$imm))]> {
2129 (!cast<Instruction>(NAME # "Xri") GPR64:$Rd, GPR64:$Rn,
2143 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
2151 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
2152 [(set GPR64:$Rd, (OpNode GPR64:$Rn,
2160 !cast<Instruction>(NAME#"Xrs"), GPR64>;
2168 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
2174 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
2175 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_shifted_reg64:$Rm))]> {
2183 !cast<Instruction>(NAME#"Xrs"), GPR64>;
2247 def Xi : BaseCondComparisonImm<op, GPR64, imm0_31, mnemonic, OpNode> {
2254 def Xr : BaseCondComparisonReg<op, GPR64, mnemonic, OpNode> {
2289 def Xr : BaseCondSelect<op, op2, GPR64, asm> {
2328 def Xr : BaseCondSelectOp<op, op2, GPR64, asm, frag> {
2336 def : Pat<(AArch64csel (frag GPR64:$Rm), GPR64:$Rn, (i32 imm:$cond), NZCV),
2337 (!cast<Instruction>(NAME # Xr) GPR64:$Rn, GPR64:$Rm,
2600 (INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
2618 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2620 (loadop (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2643 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2645 (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2690 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2692 (loadop (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2715 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2717 (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2762 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2764 (loadop (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2787 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2789 (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2834 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2836 (loadop (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2859 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2861 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2906 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2908 (loadop (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2931 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2933 (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2976 (ins prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2978 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2985 GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
3576 def UXHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR64, asm,
3577 [(set GPR64:$Rd, (OpN FPR16:$Rn))]> {
3589 def UXSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR64, asm,
3590 [(set GPR64:$Rd, (OpN FPR32:$Rn))]> {
3601 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
3602 [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3620 def SXHri : BaseFPToInteger<0b11, rmode, opcode, FPR16, GPR64,
3622 [(set GPR64:$Rd, (OpN (fmul FPR16:$Rn,
3638 def SXSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR64,
3640 [(set GPR64:$Rd, (OpN (fmul FPR32:$Rn,
3655 def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
3657 [(set GPR64:$Rd, (OpN (fmul FPR64:$Rn,
3720 def UXHri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR16, f16, asm, node> {
3726 def UXSri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR32, f32, asm, node> {
3731 def UXDri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR64, f64, asm, node> {
3765 def SXHri: BaseIntegerToFP<isUnsigned, GPR64, FPR16, fixedpoint_f16_i64, asm,
3767 (fdiv (node GPR64:$Rn),
3774 def SXSri: BaseIntegerToFP<isUnsigned, GPR64, FPR32, fixedpoint_f32_i64, asm,
3776 (fdiv (node GPR64:$Rn),
3782 def SXDri: BaseIntegerToFP<isUnsigned, GPR64, FPR64, fixedpoint_f64_i64, asm,
3784 (fdiv (node GPR64:$Rn),
3866 def XHr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR16, asm> {
3877 def XDr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR64, asm> {
3888 def HXr : BaseUnscaledConversion<0b00, 0b110, FPR16, GPR64, asm> {
3899 def DXr : BaseUnscaledConversion<0b00, 0b110, FPR64, GPR64, asm> {
3904 def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
3910 def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
6189 def vi8to64 : SIMDSMov<1, ".b", GPR64, VectorIndexB> {
6199 def vi16to64 : SIMDSMov<1, ".h", GPR64, VectorIndexH> {
6204 def vi32to64 : SIMDSMov<1, ".s", GPR64, VectorIndexS> {
6227 def vi64 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndexD> {
6237 GPR64, VectorIndexD>;
6293 def vi64gpr : SIMDInsFromMain<".d", v2i64, GPR64, VectorIndexD> {
6341 GPR64, VectorIndexD>;
9386 let Sz = 0b11, Acq = Acq, Rel = Rel in def d : BaseCAS<order, "", GPR64>;
9433 let Sz = 0b11, Acq = Acq, Rel = Rel in def d : BaseSWP<order, "", GPR64>;
9470 def d : BaseLDOPregister<op, order, "", GPR64>;
9485 def : BaseSTOPregister<asm # "l", GPR64, XZR,
9493 def : BaseSTOPregister<asm, GPR64, XZR,