308   bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));  in canFoldIntoCSel()
382   if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||  in canInsertSelect()
383       AArch64::GPR32allRegClass.hasSubClassEq(RC)) {  in canInsertSelect()
396   if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||  in canInsertSelect()
397       AArch64::FPR32RegClass.hasSubClassEq(RC)) {  in canInsertSelect()
777     } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&  in UpdateOperandRegClass()
2195     if (AArch64::FPR8RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
2199     if (AArch64::FPR16RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
2203     if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2209     } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
2213     if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2219     } else if (AArch64::FPR64RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
2223     if (AArch64::FPR128RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
2225     else if (AArch64::DDRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2233     if (AArch64::DDDRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2241     if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2246     } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2254     if (AArch64::QQQRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2262     if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
2299     if (AArch64::FPR8RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
2303     if (AArch64::FPR16RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
2307     if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
2313     } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
2317     if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
2323     } else if (AArch64::FPR64RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
2327     if (AArch64::FPR128RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
2329     else if (AArch64::DDRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
2337     if (AArch64::DDDRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
2345     if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
2350     } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
2358     if (AArch64::QQQRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
2366     if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()