185                                                unsigned Val) const {  in createRegOperand()
187   if (Val >= RegCl.getNumRegs())  in createRegOperand()
188     return errOperand(Val, Twine(getRegClassName(RegClassID)) +  in createRegOperand()
189                            ": unknown register " + Twine(Val));  in createRegOperand()
190   return createRegOperand(RegCl.getRegister(Val));  in createRegOperand()
195                                                 unsigned Val) const {  in createSRegOperand()
223   if (Val % (1 << shift))  in createSRegOperand()
225                    << ": scalar reg isn't aligned " << Val;  in createSRegOperand()
226   return createRegOperand(SRegClassID, Val >> shift);  in createSRegOperand()
229 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {  in decodeOperand_VS_32()
230   return decodeSrcOp(OPW32, Val);  in decodeOperand_VS_32()
233 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {  in decodeOperand_VS_64()
234   return decodeSrcOp(OPW64, Val);  in decodeOperand_VS_64()
237 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {  in decodeOperand_VGPR_32()
238   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);  in decodeOperand_VGPR_32()
241 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {  in decodeOperand_VReg_64()
242   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);  in decodeOperand_VReg_64()
245 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {  in decodeOperand_VReg_96()
246   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);  in decodeOperand_VReg_96()
249 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {  in decodeOperand_VReg_128()
250   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);  in decodeOperand_VReg_128()
253 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {  in decodeOperand_SReg_32()
257   return decodeSrcOp(OPW32, Val);  in decodeOperand_SReg_32()
260 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0(unsigned Val) const {  in decodeOperand_SReg_32_XM0()
262   return decodeOperand_SReg_32(Val);  in decodeOperand_SReg_32_XM0()
265 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {  in decodeOperand_SReg_64()
267   return decodeSrcOp(OPW64, Val);  in decodeOperand_SReg_64()
270 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {  in decodeOperand_SReg_128()
271   return decodeSrcOp(OPW128, Val);  in decodeOperand_SReg_128()
274 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {  in decodeOperand_SReg_256()
275   return createSRegOperand(AMDGPU::SReg_256RegClassID, Val);  in decodeOperand_SReg_256()
278 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {  in decodeOperand_SReg_512()
279   return createSRegOperand(AMDGPU::SReg_512RegClassID, Val);  in decodeOperand_SReg_512()
359 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {  in decodeSrcOp()
361   assert(Val < 512); // enum9  in decodeSrcOp()
363   if (VGPR_MIN <= Val && Val <= VGPR_MAX) {  in decodeSrcOp()
364     return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN);  in decodeSrcOp()
366   if (Val <= SGPR_MAX) {  in decodeSrcOp()
368     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);  in decodeSrcOp()
370   if (TTMP_MIN <= Val && Val <= TTMP_MAX) {  in decodeSrcOp()
371     return createSRegOperand(getTtmpClassId(Width), Val - TTMP_MIN);  in decodeSrcOp()
377   if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)  in decodeSrcOp()
378     return decodeIntImmed(Val);  in decodeSrcOp()
380   if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)  in decodeSrcOp()
381     return decodeFPImmed(Is32, Val);  in decodeSrcOp()
383   if (Val == LITERAL_CONST)  in decodeSrcOp()
386   return Is32 ? decodeSpecialReg32(Val) : decodeSpecialReg64(Val);  in decodeSrcOp()
389 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {  in decodeSpecialReg32()
391   switch (Val) {  in decodeSpecialReg32()
413   return errOperand(Val, "unknown operand encoding " + Twine(Val));  in decodeSpecialReg32()
416 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {  in decodeSpecialReg64()
418   switch (Val) {  in decodeSpecialReg64()
426   return errOperand(Val, "unknown operand encoding " + Twine(Val));  in decodeSpecialReg64()