Lines Matching refs:REG_SEQUENCE
1787 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE; in getVALUOp()
1867 case AMDGPU::REG_SEQUENCE: in canReadVGPR()
2184 get(AMDGPU::REG_SEQUENCE), DstReg); in readlaneVGPRToSGPR()
2278 if (MI.getOpcode() == AMDGPU::REG_SEQUENCE) { in legalizeOperands()
2383 BuildMI(MBB, MI, MI.getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewSRsrc) in legalizeOperands()
2411 BuildMI(MBB, MI, MI.getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr) in legalizeOperands()
2478 BuildMI(MBB, Addr64, Addr64->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), in legalizeOperands()
2734 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) in splitScalar64BitUnaryOp()
2799 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) in splitScalar64BitBinaryOp()
2889 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) in splitScalar64BitBFE()
2908 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) in splitScalar64BitBFE()
2957 case AMDGPU::REG_SEQUENCE: in getDestEquivalentVGPRClass()