Lines Matching refs:DefAlign
3187 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle()
3214 if ((isSLoad && (RegNo % 2)) || DefAlign < 8) in getVLDMDefCycle()
3228 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle()
3247 if ((RegNo % 2) || DefAlign < 8) in getLDMDefCycle()
3331 unsigned DefIdx, unsigned DefAlign, in getOperandLatency() argument
3356 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); in getOperandLatency()
3377 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); in getOperandLatency()
3497 const MCInstrDesc &DefMCID, unsigned DefAlign) { in adjustDefLatency() argument
3557 if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment()) { in adjustDefLatency()
3743 unsigned DefAlign = DefMI.hasOneMemOperand() in getOperandLatencyImpl() local
3751 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, UseMCID, in getOperandLatencyImpl()
3761 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign); in getOperandLatencyImpl()
3793 unsigned DefAlign = !DefMN->memoperands_empty() in getOperandLatency() local
3798 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, in getOperandLatency()
3859 if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment()) in getOperandLatency()
4044 unsigned DefAlign = in getInstrLatency() local
4046 int Adj = adjustDefLatency(Subtarget, MI, MCID, DefAlign); in getInstrLatency()