Lines Matching refs:hasSubClassEq

880       if (ARM::GPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
884       } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
892       if (ARM::DPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
896       } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
917       if (ARM::DPairRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
934       if (ARM::DTripleRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
954       if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
976       if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1062     if (ARM::GPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1066     } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1073     if (ARM::DPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1076     } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1101     if (ARM::DPairRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1115     if (ARM::DTripleRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1135     if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1156     if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()