1422   unsigned SrcReg1 = getRegForValue(Src1Value);  in ARMEmitCmp()  local
1423   if (SrcReg1 == 0) return false;  in ARMEmitCmp()
1433     SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);  in ARMEmitCmp()
1434     if (SrcReg1 == 0) return false;  in ARMEmitCmp()
1442   SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);  in ARMEmitCmp()
1446                     .addReg(SrcReg1).addReg(SrcReg2));  in ARMEmitCmp()
1450       .addReg(SrcReg1);  in ARMEmitCmp()
1758   unsigned SrcReg1 = getRegForValue(I->getOperand(0));  in SelectBinaryIntOp()  local
1759   if (SrcReg1 == 0) return false;  in SelectBinaryIntOp()
1767   SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);  in SelectBinaryIntOp()
1771                   .addReg(SrcReg1).addReg(SrcReg2));  in SelectBinaryIntOp()