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Lines Matching refs:createResultReg

281   unsigned ResultReg = createResultReg(RC);  in fastEmitInst_r()
304 unsigned ResultReg = createResultReg(RC); in fastEmitInst_rr()
332 unsigned ResultReg = createResultReg(RC); in fastEmitInst_ri()
359 unsigned ResultReg = createResultReg(RC); in fastEmitInst_rri()
387 unsigned ResultReg = createResultReg(RC); in fastEmitInst_i()
408 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToFPReg()
418 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToIntReg()
444 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
460 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
483 unsigned ImmReg = createResultReg(RC); in ARMMaterializeInt()
499 unsigned ImmReg = createResultReg(RC); in ARMMaterializeInt()
525 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
552 unsigned DestReg = createResultReg(RC); in ARMMaterializeGV()
614 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
628 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
680 unsigned ResultReg = createResultReg(RC); in fastMaterializeAlloca()
855 unsigned ResultReg = createResultReg(RC); in ARMSimplifyAddress()
1003 ResultReg = createResultReg(RC); in ARMEmitLoad()
1012 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32)); in ARMEmitLoad()
1065 unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass in ARMEmitStore()
1115 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32)); in ARMEmitStore()
1484 unsigned DestReg = createResultReg(RC); in SelectCmp()
1507 unsigned Result = createResultReg(&ARM::DPRRegClass); in SelectFPExt()
1526 unsigned Result = createResultReg(&ARM::SPRRegClass); in SelectFPTrunc()
1571 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP()
1597 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); in SelectFPToI()
1663 unsigned ResultReg = createResultReg(RC); in SelectSelect()
1766 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); in SelectBinaryIntOp()
1814 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); in SelectBinaryFPOp()
2037 unsigned ResultReg = createResultReg(DstRC); in FinishCall()
2058 unsigned ResultReg = createResultReg(DstRC); in FinishCall()
2496 DestReg = createResultReg(RC); in SelectIntrinsicCall()
2700 ResultReg = createResultReg(RC); in ARMEmitIntExt()
2782 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); in SelectShift()
2960 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMLowerPICELF()
2971 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMLowerPICELF()
3048 unsigned ResultReg = createResultReg(RC); in fastLowerArguments()