Lines Matching refs:BITCAST
901 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in ARMTargetLowering()
1518 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); in LowerCallResult()
1666 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
2296 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerReturn()
2424 } else if (Copy->getOpcode() == ISD::BITCAST) { in isUsedByReturnOnly()
3323 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
3407 } else if (Op->getOpcode() == ISD::BITCAST && in isFloatingPointZero()
4249 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || in LowerFCOPYSIGN()
4261 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), in LowerFCOPYSIGN()
4269 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), in LowerFCOPYSIGN()
4273 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), in LowerFCOPYSIGN()
4275 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); in LowerFCOPYSIGN()
4276 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); in LowerFCOPYSIGN()
4282 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); in LowerFCOPYSIGN()
4288 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res); in LowerFCOPYSIGN()
4292 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res); in LowerFCOPYSIGN()
4302 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1); in LowerFCOPYSIGN()
4310 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); in LowerFCOPYSIGN()
4311 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, in LowerFCOPYSIGN()
4445 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc); in CombineVMOVDRRCandidateWithVecOp()
4478 return DAG.getNode(ISD::BITCAST, dl, DstVT, in ExpandBITCAST()
4512 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); in getZeroVector()
4657 SDValue BitsVT8 = DAG.getNode(ISD::BITCAST, dl, VT8Bit, Bits); in LowerCTTZ()
4707 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0)); in getCTPOP16BitCounts()
4765 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0)); in lowerCTPOP32BitElements()
4954 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST) in LowerVSETCC()
4959 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0)); in LowerVSETCC()
4960 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1)); in LowerVSETCC()
5229 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant); in LowerConstantFP()
5232 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32, in LowerConstantFP()
5246 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant); in LowerConstantFP()
5249 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32, in LowerConstantFP()
5666 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); in LowerBUILD_VECTOR()
5677 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); in LowerBUILD_VECTOR()
5790 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32, in LowerBUILD_VECTOR()
5796 return DAG.getNode(ISD::BITCAST, dl, VT, Val); in LowerBUILD_VECTOR()
5828 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i))); in LowerBUILD_VECTOR()
5830 return DAG.getNode(ISD::BITCAST, dl, VT, Val); in LowerBUILD_VECTOR()
6000 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec); in ReconstructShuffle()
6054 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); in ReconstructShuffle()
6362 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); in LowerVECTOR_SHUFFLE()
6363 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); in LowerVECTOR_SHUFFLE()
6375 return DAG.getNode(ISD::BITCAST, dl, VT, Val); in LowerVECTOR_SHUFFLE()
6424 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0), in LowerCONCAT_VECTORS()
6428 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1), in LowerCONCAT_VECTORS()
6430 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val); in LowerCONCAT_VECTORS()
6440 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) { in isExtendedBUILD_VECTOR()
6586 if (N->getOpcode() == ISD::BITCAST) { in SkipExtensionForVMULL()
6705 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
6707 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
6731 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
6734 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
6769 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
6772 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
6880 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerUDIV()
6883 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerUDIV()
7176 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG); in LowerOperation()
7242 case ISD::BITCAST: in ReplaceNodeResults()
9247 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0)); in PerformANDCombine()
9249 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic); in PerformANDCombine()
9289 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0)); in PerformORCombine()
9291 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr); in PerformORCombine()
9337 return DAG.getNode(ISD::BITCAST, dl, VT, Result); in PerformORCombine()
9661 if (Op0.getOpcode() == ISD::BITCAST) in PerformVMOVDRRCombine()
9663 if (Op1.getOpcode() == ISD::BITCAST) in PerformVMOVDRRCombine()
9668 return DAG.getNode(ISD::BITCAST, SDLoc(N), in PerformVMOVDRRCombine()
9710 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i)); in PerformBUILD_VECTORCombine()
9717 return DAG.getNode(ISD::BITCAST, dl, VT, BV); in PerformBUILD_VECTORCombine()
9747 if (Use->getOpcode() != ISD::BITCAST || in PerformARMBUILD_VECTORCombine()
9761 if (Elt->getOpcode() == ISD::BITCAST) { in PerformARMBUILD_VECTORCombine()
9794 if (V.getOpcode() == ISD::BITCAST && in PerformARMBUILD_VECTORCombine()
9799 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V); in PerformARMBUILD_VECTORCombine()
9806 Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec); in PerformARMBUILD_VECTORCombine()
9828 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0)); in PerformInsertEltCombine()
9829 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1)); in PerformInsertEltCombine()
9835 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt); in PerformInsertEltCombine()
10072 StVal = DAG.getNode(ISD::BITCAST, dl, AlignedVecTy, StVal); in CombineBaseUpdate()
10088 LdVal = DAG.getNode(ISD::BITCAST, dl, VecTy, LdVal); in CombineBaseUpdate()
10202 while (Op.getOpcode() == ISD::BITCAST) in PerformVDUPLANECombine()
10218 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op); in PerformVDUPLANECombine()
10271 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal); in PerformSTORECombine()
10301 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff); in PerformSTORECombine()
10358 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec); in PerformSTORECombine()
10362 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt); in PerformSTORECombine()
10502 while (Op.getOpcode() == ISD::BITCAST) in getVShiftImm()