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Lines Matching refs:NewVReg1

7322     unsigned NewVReg1 = MRI->createVirtualRegister(TRC);  in SetupEntryBlockForSjLj()  local
7323 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1) in SetupEntryBlockForSjLj()
7330 .addReg(NewVReg1, RegState::Kill) in SetupEntryBlockForSjLj()
7349 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj() local
7350 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1) in SetupEntryBlockForSjLj()
7355 .addReg(NewVReg1, RegState::Kill) in SetupEntryBlockForSjLj()
7381 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj() local
7382 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1) in SetupEntryBlockForSjLj()
7388 .addReg(NewVReg1, RegState::Kill) in SetupEntryBlockForSjLj()
7505 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() local
7506 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1) in EmitSjLjDispatchBlock()
7513 .addReg(NewVReg1) in EmitSjLjDispatchBlock()
7529 .addReg(NewVReg1) in EmitSjLjDispatchBlock()
7547 .addReg(NewVReg1) in EmitSjLjDispatchBlock()
7552 .addReg(NewVReg1) in EmitSjLjDispatchBlock()
7555 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() local
7556 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1) in EmitSjLjDispatchBlock()
7563 .addReg(NewVReg1) in EmitSjLjDispatchBlock()
7581 .addReg(NewVReg1) in EmitSjLjDispatchBlock()
7593 .addReg(NewVReg1) in EmitSjLjDispatchBlock()
7628 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() local
7629 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1) in EmitSjLjDispatchBlock()
7636 .addReg(NewVReg1) in EmitSjLjDispatchBlock()
7652 .addReg(NewVReg1) in EmitSjLjDispatchBlock()
7671 .addReg(NewVReg1) in EmitSjLjDispatchBlock()
7683 .addReg(NewVReg1) in EmitSjLjDispatchBlock()