Lines Matching refs:QPR
625 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
627 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
631 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
635 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1026 : PseudoNLdSt<(outs QPR:$dst),
1027 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1030 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1031 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1076 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1100 def : Pat<(vector_insert (v4f32 QPR:$src),
1102 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1614 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1617 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1621 (ins addrmode6:$addr, QPR:$src), itin,
1625 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
2028 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
2032 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
2061 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2087 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
2088 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
2104 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2369 def : Pat<(dword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2370 (VST1q64 addrmode6:$addr, QPR:$value)>;
2373 def : Pat<(word_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2374 (VST1q32 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2377 def : Pat<(hword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2378 (VST1q16 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2381 def : Pat<(byte_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2382 (VST1q8 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2442 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2443 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2444 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2458 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2459 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2460 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2473 : N2Vnp<op19_18, op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
2475 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2481 : N2Vnp<op19_18, op17_16, op10_8, op7, op6, (outs QPR:$Vd), (ins QPR:$Vm),
2483 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2490 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vm),
2492 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vm))))]> {
2502 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2503 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2511 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2512 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2519 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2521 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2528 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2530 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2540 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2541 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2600 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2602 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2611 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2613 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2622 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2624 [(set (ResTy QPR:$Vd),
2625 (ResTy (ShOp (ResTy QPR:$Vn),
2635 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2637 [(set (ResTy QPR:$Vd),
2638 (ResTy (ShOp (ResTy QPR:$Vn),
2704 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2706 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2717 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
2718 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2726 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm),
2728 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vn),
2729 (OpTy QPR:$Vm))))]> {
2737 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2739 [(set (ResTy QPR:$Vd),
2740 (ResTy (IntOp (ResTy QPR:$Vn),
2749 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2751 [(set (ResTy QPR:$Vd),
2752 (ResTy (IntOp (ResTy QPR:$Vn),
2761 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2763 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2809 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2811 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2812 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2817 (outs QPR:$Vd),
2818 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2821 [(set (ResTy QPR:$Vd),
2822 (ResTy (ShOp (ResTy QPR:$src1),
2823 (ResTy (MulOp QPR:$Vn,
2831 (outs QPR:$Vd),
2832 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2835 [(set (ResTy QPR:$Vd),
2836 (ResTy (ShOp (ResTy QPR:$src1),
2837 (ResTy (MulOp QPR:$Vn,
2854 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2856 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2857 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2873 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2875 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2876 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2883 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2885 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2891 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2892 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2895 [(set QPR:$Vd,
2896 (OpNode (TyQ QPR:$src1),
2903 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2904 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2907 [(set QPR:$Vd,
2908 (OpNode (TyQ QPR:$src1),
2919 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2921 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2931 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2933 [(set QPR:$Vd,
2934 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2939 (outs QPR:$Vd),
2940 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2943 [(set (ResTy QPR:$Vd),
2944 (ResTy (IntOp (ResTy QPR:$src1),
2952 (outs QPR:$Vd),
2953 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2956 [(set (ResTy QPR:$Vd),
2957 (ResTy (IntOp (ResTy QPR:$src1),
2967 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2969 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2978 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2980 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2988 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2990 [(set QPR:$Vd,
2997 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2999 [(set QPR:$Vd,
3009 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3011 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3022 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3024 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3034 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3036 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
3046 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
3047 [(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
3053 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3055 [(set (ResTy QPR:$Vd),
3063 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3065 [(set (ResTy QPR:$Vd),
3075 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
3077 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
3096 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
3097 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3098 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
3116 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
3118 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
3134 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
3136 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
3145 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3147 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), ImmTy:$SIMM)))]>;
3155 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3157 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
3174 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3175 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3177 [(set QPR:$Vd, (Ty (add QPR:$src1,
3178 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
3194 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3195 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
3197 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
3213 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3215 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
3263 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3265 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
3267 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3269 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
3271 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3273 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
3275 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3277 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
3281 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3283 [(set QPR:$Vd, (v8i16 (OpNode (v8f16 QPR:$Vm))))]>,
4163 def : Pat<(v8i8 (trunc (NEONvshru (add (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4164 (VADDHNv8i8 QPR:$Vn, QPR:$Vm)>;
4165 def : Pat<(v4i16 (trunc (NEONvshru (add (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4166 (VADDHNv4i16 QPR:$Vn, QPR:$Vm)>;
4167 def : Pat<(v2i32 (trunc (NEONvshru (add (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4168 (VADDHNv2i32 QPR:$Vn, QPR:$Vm)>;
4199 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
4200 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
4201 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
4202 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4205 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
4206 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
4207 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
4208 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4211 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
4212 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
4213 (v4f32 (VMULslfq (v4f32 QPR:$src1),
4214 (v2f32 (EXTRACT_SUBREG QPR:$src2,
4223 def : Pat<(v4f32 (fmul QPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4224 (VMULslfq QPR:$Rn,
4236 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
4237 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4239 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
4240 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4243 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
4244 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4246 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
4247 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4258 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
4259 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4261 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
4262 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4265 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
4266 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4268 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
4269 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4327 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
4328 (mul (v8i16 QPR:$src2),
4329 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4330 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4331 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4335 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
4336 (mul (v4i32 QPR:$src2),
4337 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4338 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4339 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4343 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
4344 (fmul_su (v4f32 QPR:$src2),
4345 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4346 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
4347 (v4f32 QPR:$src2),
4348 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4380 (v8i16 QPR:$src1),
4381 (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$Vn),
4382 (v8i16 QPR:$Vm))))),
4383 (v8i16 (VQRDMLAHv8i16 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4385 (v4i32 QPR:$src1),
4386 (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$Vn),
4387 (v4i32 QPR:$Vm))))),
4388 (v4i32 (VQRDMLAHv4i32 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4410 (v8i16 QPR:$src1),
4412 (v8i16 QPR:$src2),
4413 (v8i16 (NEONvduplane (v8i16 QPR:$src3),
4415 (v8i16 (VQRDMLAHslv8i16 (v8i16 QPR:$src1),
4416 (v8i16 QPR:$src2),
4418 QPR:$src3,
4422 (v4i32 QPR:$src1),
4424 (v4i32 QPR:$src2),
4425 (v4i32 (NEONvduplane (v4i32 QPR:$src3),
4427 (v4i32 (VQRDMLAHslv4i32 (v4i32 QPR:$src1),
4428 (v4i32 QPR:$src2),
4430 QPR:$src3,
4450 (v8i16 QPR:$src1),
4451 (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$Vn),
4452 (v8i16 QPR:$Vm))))),
4453 (v8i16 (VQRDMLSHv8i16 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4455 (v4i32 QPR:$src1),
4456 (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$Vn),
4457 (v4i32 QPR:$Vm))))),
4458 (v4i32 (VQRDMLSHv4i32 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4479 (v8i16 QPR:$src1),
4481 (v8i16 QPR:$src2),
4482 (v8i16 (NEONvduplane (v8i16 QPR:$src3),
4484 (v8i16 (VQRDMLSHslv8i16 (v8i16 QPR:$src1),
4485 (v8i16 QPR:$src2),
4487 QPR:$src3,
4491 (v4i32 QPR:$src1),
4493 (v4i32 QPR:$src2),
4494 (v4i32 (NEONvduplane (v4i32 QPR:$src3),
4496 (v4i32 (VQRDMLSHslv4i32 (v4i32 QPR:$src1),
4497 (v4i32 QPR:$src2),
4499 QPR:$src3,
4508 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4511 (VQDMLALv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4512 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4515 (VQDMLALv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4516 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4520 (VQDMLALslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4521 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4525 (VQDMLALslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4557 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
4558 (mul (v8i16 QPR:$src2),
4559 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4560 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4561 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4565 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
4566 (mul (v4i32 QPR:$src2),
4567 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4568 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4569 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4573 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
4574 (fmul_su (v4f32 QPR:$src2),
4575 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4576 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
4577 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4596 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4599 (VQDMLSLv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4600 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4603 (VQDMLSLv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4604 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4608 (VQDMLSLslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4609 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4613 (VQDMLSLslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4649 def : Pat<(v4f32 (fma QPR:$Vn, QPR:$Vm, QPR:$src1)),
4650 (VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4655 def : Pat<(v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1)),
4656 (VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4702 def : Pat<(v8i8 (trunc (NEONvshru (sub (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4703 (VSUBHNv8i8 QPR:$Vn, QPR:$Vm)>;
4704 def : Pat<(v4i16 (trunc (NEONvshru (sub (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4705 (VSUBHNv4i16 QPR:$Vn, QPR:$Vm)>;
4706 def : Pat<(v2i32 (trunc (NEONvshru (sub (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4707 (VSUBHNv2i32 QPR:$Vn, QPR:$Vm)>;
4804 (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4808 (VACGEfq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4813 (VACGThq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4817 (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4823 (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4827 (VACGEfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4832 (VACGThq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4836 (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4884 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4887 [(set QPR:$Vd,
4888 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4893 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4896 [(set QPR:$Vd,
4897 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4909 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4910 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4912 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4913 (vnotq QPR:$Vm))))]>;
4935 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4938 [(set QPR:$Vd,
4939 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4944 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4947 [(set QPR:$Vd,
4948 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4958 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4959 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4961 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4962 (vnotq QPR:$Vm))))]>;
4975 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4978 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4989 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4992 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
5003 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
5005 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
5007 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
5047 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5048 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5051 [(set QPR:$Vd,
5052 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
5054 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 QPR:$src1),
5055 (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))),
5056 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
5058 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 QPR:$src1),
5059 (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))),
5060 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
5062 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 QPR:$src1),
5063 (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))),
5064 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
5066 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 QPR:$src1),
5067 (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))),
5068 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
5070 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 QPR:$src1),
5071 (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))),
5072 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
5075 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
5076 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5077 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
5079 def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd),
5080 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5081 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
5093 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5107 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5470 def : Pat<(v8i8 (trunc (NEONvshru (v8i16 QPR:$Vn), shr_imm8:$amt))),
5471 (VSHRNv8i8 QPR:$Vn, shr_imm8:$amt)>;
5472 def : Pat<(v4i16 (trunc (NEONvshru (v4i32 QPR:$Vn), shr_imm16:$amt))),
5473 (VSHRNv4i16 QPR:$Vn, shr_imm16:$amt)>;
5474 def : Pat<(v2i32 (trunc (NEONvshru (v2i64 QPR:$Vn), shr_imm32:$amt))),
5475 (VSHRNv2i32 QPR:$Vn, shr_imm32:$amt)>;
5581 def : Pat<(xor (v4i32 (bitconvert (v16i8 (NEONvshrs QPR:$src, (i32 7))))),
5582 (v4i32 (bitconvert (v16i8 (add QPR:$src,
5583 (NEONvshrs QPR:$src, (i32 7))))))),
5584 (VABSv16i8 QPR:$src)>;
5585 def : Pat<(xor (v4i32 (bitconvert (v8i16 (NEONvshrs QPR:$src, (i32 15))))),
5586 (v4i32 (bitconvert (v8i16 (add QPR:$src,
5587 (NEONvshrs QPR:$src, (i32 15))))))),
5588 (VABSv8i16 QPR:$src)>;
5589 def : Pat<(xor (v4i32 (NEONvshrs QPR:$src, (i32 31))),
5590 (v4i32 (add QPR:$src, (NEONvshrs QPR:$src, (i32 31))))),
5591 (VABSv4i32 QPR:$src)>;
5610 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
5612 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
5628 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
5630 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
5637 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
5639 [(set QPR:$Vd, (v8f16 (fneg QPR:$Vm)))]>,
5645 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
5646 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
5647 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
5678 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
5688 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
5700 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
5703 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
5712 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
5715 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
5726 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
5729 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
5737 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
5740 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
5746 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
5749 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
5765 (VMOVv16i8 QPR:$Vd, nImmVMOVI16ByteReplicate:$Vm, pred:$p)>;
5767 (VMOVv16i8 QPR:$Vd, nImmVMOVI32ByteReplicate:$Vm, pred:$p)>;
5778 (VMOVv16i8 QPR:$Vd, nImmVMVNI16ByteReplicate:$Vm, pred:$p)>;
5780 (VMOVv16i8 QPR:$Vd, nImmVMVNI32ByteReplicate:$Vm, pred:$p)>;
5795 def VMOVQ0 : ARMPseudoExpand<(outs QPR:$Vd), (ins), 4, IIC_VMOVImm,
5796 [(set QPR:$Vd, (v4i32 NEONimmAllZerosV))],
5797 (VMOVv4i32 QPR:$Vd, 0, (ops 14, zero_reg))>,
5844 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
5845 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5848 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
5849 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5852 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
5853 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5856 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
5857 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5860 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5861 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
5869 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5871 (i32 (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5876 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
5877 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
5879 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
5880 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5881 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
5882 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5916 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
5917 (v16i8 (INSERT_SUBREG QPR:$src1,
5918 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
5922 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
5923 (v8i16 (INSERT_SUBREG QPR:$src1,
5924 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
5928 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
5929 (v4i32 (INSERT_SUBREG QPR:$src1,
5930 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
5938 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
5939 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
5942 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5943 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5944 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5945 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5981 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
5983 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
6014 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
6016 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
6052 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
6053 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
6056 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
6057 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
6060 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
6061 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
6064 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
6065 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
6225 (VCVTf2sq QPR:$Qd, QPR:$Qm, pred:$p)>;
6227 (VCVTf2uq QPR:$Qd, QPR:$Qm, pred:$p)>;
6229 (VCVTs2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
6231 (VCVTu2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
6243 (VCVTh2sq QPR:$Qd, QPR:$Qm, pred:$p)>;
6245 (VCVTh2uq QPR:$Qd, QPR:$Qm, pred:$p)>;
6247 (VCVTs2hq QPR:$Qd, QPR:$Qm, pred:$p)>;
6249 (VCVTu2hq QPR:$Qd, QPR:$Qm, pred:$p)>;
6272 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
6273 (ins QPR:$Vm), IIC_VMOVQ,
6275 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
6285 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
6295 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
6296 (ins QPR:$Vm), IIC_VMOVQ,
6298 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
6314 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
6315 (ins QPR:$Vm), IIC_VMOVQ,
6317 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
6327 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
6328 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
6358 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
6359 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
6361 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
6362 (Ty QPR:$Vm), imm:$index)))]> {
6399 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
6400 (v4f32 QPR:$Vm),
6402 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
6531 (!cast<Instruction>(NAME#"Qf") QPR:$Qd, QPR:$Qm)>;
6536 (!cast<Instruction>(NAME#"Qh") QPR:$Qd, QPR:$Qm)>;
6694 def : VFPPat<(f64 (sint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
6695 (VSITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6698 def : VFPPat<(f64 (uint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
6699 (VUITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6754 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
6755 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
6756 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
6758 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
6760 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
6761 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
6762 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
6763 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
6764 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
6766 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
6768 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
6769 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
6770 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
6771 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
6772 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
6773 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
6774 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
6775 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
6776 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
6777 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
6778 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
6780 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
6782 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
6783 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
6784 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
6786 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
6788 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
6789 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
6790 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
6791 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
6824 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (VREV64q32 QPR:$src)>;
6825 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (VREV64q16 QPR:$src)>;
6826 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (VREV64q8 QPR:$src)>;
6827 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (VREV64q32 QPR:$src)>;
6828 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (VREV64q32 QPR:$src)>;
6829 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (VREV32q16 QPR:$src)>;
6830 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (VREV32q8 QPR:$src)>;
6831 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (VREV64q32 QPR:$src)>;
6832 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (VREV64q16 QPR:$src)>;
6833 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (VREV32q16 QPR:$src)>;
6834 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (VREV16q8 QPR:$src)>;
6835 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (VREV64q16 QPR:$src)>;
6836 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (VREV32q16 QPR:$src)>;
6837 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (VREV64q8 QPR:$src)>;
6838 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (VREV32q8 QPR:$src)>;
6839 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (VREV16q8 QPR:$src)>;
6840 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (VREV64q8 QPR:$src)>;
6841 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (VREV32q8 QPR:$src)>;
6842 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (VREV64q32 QPR:$src)>;
6843 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (VREV32q16 QPR:$src)>;
6844 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (VREV32q8 QPR:$src)>;
6845 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (VREV64q32 QPR:$src)>;
6846 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (VREV64q32 QPR:$src)>;
6847 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (VREV64q16 QPR:$src)>;
6848 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (VREV64q8 QPR:$src)>;
6849 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (VREV64q32 QPR:$src)>;
7145 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7149 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7153 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7157 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7162 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
7166 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
7170 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
7177 (VBICiv8i16 QPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>;
7179 (VBICiv4i32 QPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>;
8021 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
8026 (VMVNq QPR:$Vd, QPR:$Vm, pred:$p)>;
8049 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
8051 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
8053 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
8055 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
8057 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
8059 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
8061 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
8064 (VCGEhq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
8087 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
8089 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
8091 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
8093 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
8095 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
8097 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
8099 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
8102 (VCGThq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
8108 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
8118 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8120 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8122 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8128 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
8132 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
8179 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;